/** @file
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PCH Serial IO UART Lib implementation.
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All function in this library is available for PEI, DXE, and SMM,
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But do not support UEFI RUNTIME environment call.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/BaseLib.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchSerialIoLib.h>
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#include <Library/PchSerialIoUartLib.h>
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#include <IndustryStandard/Pci30.h>
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#define MAX_BAUD_RATE 115200
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#define R_PCH_SERIAL_IO_8BIT_UART_RXBUF 0x00
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#define R_PCH_SERIAL_IO_8BIT_UART_TXBUF 0x00
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#define R_PCH_SERIAL_IO_8BIT_UART_BAUD_LOW 0x00
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#define R_PCH_SERIAL_IO_8BIT_UART_BAUD_HIGH 0x01
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#define R_PCH_SERIAL_IO_8BIT_UART_FCR 0x02
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#define R_PCH_SERIAL_IO_8BIT_UART_IIR 0x02
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#define R_PCH_SERIAL_IO_8BIT_UART_LCR 0x03
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#define R_PCH_SERIAL_IO_8BIT_UART_MCR 0x04
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#define R_PCH_SERIAL_IO_8BIT_UART_LSR 0x05
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#define R_PCH_SERIAL_IO_8BIT_UART_USR 0x1F
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#define R_PCH_SERIAL_IO_32BIT_UART_CTR 0xFC //Component Type Register contains identification code
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#define UART_COMPONENT_IDENTIFICATION_CODE 0x44570110
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#define B_PCH_SERIAL_IO_UART_IIR_FIFOSE BIT7|BIT6
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#define B_PCH_SERIAL_IO_UART_LSR_RXDA BIT0
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#define B_PCH_SERIAL_IO_UART_LSR_BI BIT4
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#define B_PCH_SERIAL_IO_UART_LSR_TXRDY BIT5
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#define B_PCH_SERIAL_IO_UART_LCR_DLAB BIT7
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#define B_PCH_SERIAL_IO_UART_FCR_FCR BIT0
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#define B_PCH_SERIAL_IO_UART_MCR_RTS BIT1
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#define B_PCH_SERIAL_IO_UART_MCR_AFCE BIT5
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#define B_PCH_SERIAL_IO_UART_USR_TFNF BIT1
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/**
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Returns UART's currently active access mode, 8 or 32 bit
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@param[in] MmioBase Base address of UART MMIO space
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@retval AccessMode8bit
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@retval AccessMode32bit
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**/
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UART_ACCESS_MODE
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DetectAccessMode (
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IN UINTN MmioBase
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)
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{
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if (MmioRead32 (MmioBase + R_PCH_SERIAL_IO_32BIT_UART_CTR) == UART_COMPONENT_IDENTIFICATION_CODE) {
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return AccessMode32bit;
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} else {
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return AccessMode8bit;
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}
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}
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/**
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Register access helper. Depending on SerialIO UART mode,
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its registers are aligned to 1 or 4 bytes and have 8 or 32bit size
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@param[in] AccessMode Selects between 8bit access to 1-byte aligned registers or 32bit access to 4-byte algined
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@param[in] BaseAddress Base address of UART MMIO space
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@param[in] Offset Register offset in 8bit mode
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@param[in] Data Data to be written
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**/
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STATIC
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VOID
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WriteRegister (
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IN UART_ACCESS_MODE AccessMode,
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IN UINTN BaseAddress,
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IN UINTN Offset,
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IN UINT8 Data
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)
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{
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if (AccessMode == AccessMode32bit) {
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MmioWrite32 (BaseAddress + 4*Offset, Data);
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} else {
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MmioWrite8 (BaseAddress + Offset, Data);
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}
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}
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/**
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Register access helper. Depending on SerialIO UART mode,
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its registers are aligned to 1 or 4 bytes and have 8 or 32bit size
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@param[in] AccessMode Selects between 8bit access to 1-byte aligned registers or 32bit access to 4-byte algined
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@param[in] BaseAddress Base address of UART MMIO space
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@param[in] Offset Register offset in 8bit mode
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@retval retrieved register value, always 8bit regardless of access mode
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**/
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STATIC
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UINT8
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ReadRegister (
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IN UART_ACCESS_MODE AccessMode,
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IN UINTN BaseAddress,
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IN UINTN Offset
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)
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{
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if (AccessMode == AccessMode32bit) {
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return (UINT8) (0xFF & MmioRead32 (BaseAddress + 4*Offset));
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} else {
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return MmioRead8 (BaseAddress + Offset);
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}
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}
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/**
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SerialIo UART in PCI mode will become unavailable when PCI enumerator
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disables its memory space. This function re-enables it
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@param[in] UartNumber Selects Serial IO UART device (0-2)
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**/
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STATIC
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VOID
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EnablePciMse (
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IN UINT8 UartNumber
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)
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{
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UINTN CfgSpace;
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CfgSpace = FindSerialIoBar (UartNumber + PchSerialIoIndexUart0, 1);
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if (MmioRead16 (CfgSpace + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
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return;
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}
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if ((MmioRead16 (CfgSpace + PCI_COMMAND_OFFSET) & EFI_PCI_COMMAND_MEMORY_SPACE) != EFI_PCI_COMMAND_MEMORY_SPACE) {
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if ((MmioRead32 (CfgSpace + PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000) != 0x0 &&
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(MmioRead32 (CfgSpace + PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000) != 0xFFFFF000 ) {
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MmioOr8 (CfgSpace + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
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}
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}
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}
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/**
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Initialize selected SerialIo UART.
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This init function MUST be used prior any SerialIo UART functions to init serial io controller if platform is going use serialio UART as debug output.
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@param UartNumber Selects Serial IO UART device (0-2)
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@param FifoEnable When TRUE, enables 64-byte FIFOs.
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@param BaudRate Baud rate.
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@param LineControl Data length, parity, stop bits.
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@param HardwareFlowControl Automated hardware flow control. If TRUE, hardware automatically checks CTS when sending data, and sets RTS when receiving data.
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**/
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VOID
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EFIAPI
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PchSerialIoUartInit (
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UINT8 UartNumber,
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BOOLEAN FifoEnable,
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UINT32 BaudRate,
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UINT8 LineControl,
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BOOLEAN HardwareFlowControl
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)
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{
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UINTN Base;
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UINTN Divisor;
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UART_ACCESS_MODE AccessMode;
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Base = FindSerialIoBar (UartNumber + PchSerialIoIndexUart0, 0);
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if ((Base & 0xFFFFFF00) == 0x0 || (Base & 0xFFFFF000) == 0xFFFFF000) {
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//
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// Base is not programmed, skip it.
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//
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return;
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}
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EnablePciMse (UartNumber);
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AccessMode = DetectAccessMode (Base);
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Divisor = MAX_BAUD_RATE / BaudRate;
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//
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// Configure baud rate
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//
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WriteRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_LCR, B_PCH_SERIAL_IO_UART_LCR_DLAB);
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WriteRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
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WriteRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
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//
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// Configure Line control and switch back to bank 0
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//
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WriteRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_LCR, LineControl & 0x1F);
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//
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// Enable and reset FIFOs
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//
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WriteRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_FCR, FifoEnable?B_PCH_SERIAL_IO_UART_FCR_FCR:0 );
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//
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// Put Modem Control Register(MCR) into its reset state of 0x00.
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//
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WriteRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_MCR, B_PCH_SERIAL_IO_UART_MCR_RTS | (HardwareFlowControl?B_PCH_SERIAL_IO_UART_MCR_AFCE:0));
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}
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/**
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Write data to serial device.
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If the buffer is NULL, then return 0;
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if NumberOfBytes is zero, then return 0.
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@param UartNumber Selects Serial IO UART device (0-2)
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@param Buffer Point of data buffer which need to be writed.
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@param NumberOfBytes Number of output bytes which are cached in Buffer.
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@retval Actual number of bytes writed to serial device.
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**/
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UINTN
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EFIAPI
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PchSerialIoUartOut (
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IN UINT8 UartNumber,
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IN UINT8 *Buffer,
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IN UINTN NumberOfBytes
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)
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{
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UINTN BytesLeft;
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UINTN Base;
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UART_ACCESS_MODE AccessMode;
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if (NULL == Buffer) {
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return 0;
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}
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Base = FindSerialIoBar (UartNumber + PchSerialIoIndexUart0, 0);
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//
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// Sanity checks to avoid infinite loop when trying to print through uninitialized UART
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//
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if ((Base & 0xFFFFFF00) == 0x0 || (Base & 0xFFFFF000) == 0xFFFFF000) {
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return 0;
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}
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EnablePciMse (UartNumber);
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AccessMode = DetectAccessMode (Base);
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if (ReadRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_USR) == 0xFF) {
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return 0;
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}
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BytesLeft = NumberOfBytes;
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while (BytesLeft != 0) {
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//
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// Write data while there's room in TXFIFO. If HW Flow Control was enabled, it happens automatically on hardware level.
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//
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if (ReadRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_USR) & B_PCH_SERIAL_IO_UART_USR_TFNF) {
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WriteRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_TXBUF, *Buffer);
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Buffer++;
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BytesLeft--;
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}
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}
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return NumberOfBytes;
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}
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/*
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Read data from serial device and save the datas in buffer.
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If the buffer is NULL, then return 0;
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if NumberOfBytes is zero, then return 0.
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@param UartNumber Selects Serial IO UART device (0-2)
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@param Buffer Point of data buffer which need to be writed.
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@param NumberOfBytes Number of output bytes which are cached in Buffer.
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@param WaitUntilBufferFull When TRUE, function waits until whole buffer is filled. When FALSE, function returns as soon as no new characters are available.
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@retval Actual number of bytes raed to serial device.
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**/
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UINTN
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EFIAPI
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PchSerialIoUartIn (
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IN UINT8 UartNumber,
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OUT UINT8 *Buffer,
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IN UINTN NumberOfBytes,
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IN BOOLEAN WaitUntilBufferFull
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)
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{
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UINTN BytesReceived;
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UINTN Base;
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UART_ACCESS_MODE AccessMode;
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UINT8 Lsr;
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UINT8 Byte;
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if (NULL == Buffer) {
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return 0;
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}
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Base = FindSerialIoBar (UartNumber + PchSerialIoIndexUart0, 0);
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//
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// Sanity checks to avoid infinite loop when trying to print through uninitialized UART
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//
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if ((Base & 0xFFFFFF00) == 0x0 || (Base & 0xFFFFF000) == 0xFFFFF000) {
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return 0;
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}
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EnablePciMse (UartNumber);
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AccessMode = DetectAccessMode (Base);
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BytesReceived = 0;
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while (BytesReceived != NumberOfBytes) {
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//
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// Read the line status register
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//
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Lsr = ReadRegister(AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_LSR);
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//
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// If there is data in the RX buffer, read it.
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//
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if ((Lsr & B_PCH_SERIAL_IO_UART_LSR_RXDA) != 0) {
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Byte = ReadRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_RXBUF);
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//
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// Check if the break interrupt bit is set. If set, the byte read from the
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// RX buffer is invalid and should be ignored. If not set, copy the byte into
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// the receive buffer.
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//
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if ((Lsr & B_PCH_SERIAL_IO_UART_LSR_BI) == 0) {
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*Buffer = Byte;
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Buffer++;
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BytesReceived++;
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}
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} else {
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if (!WaitUntilBufferFull) {
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//
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// If there's no data and function shouldn't wait, exit early
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//
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return BytesReceived;
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}
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}
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}
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return BytesReceived;
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}
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/**
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Polls a serial device to see if there is any data waiting to be read.
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Polls a serial device to see if there is any data waiting to be read.
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If there is data waiting to be read from the serial device, then TRUE is returned.
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If there is no data waiting to be read from the serial device, then FALSE is returned.
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@param UartNumber Selects Serial IO UART device (0-2)
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@retval TRUE Data is waiting to be read from the serial device.
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@retval FALSE There is no data waiting to be read from the serial device.
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**/
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BOOLEAN
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EFIAPI
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PchSerialIoUartPoll (
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IN UINT8 UartNumber
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)
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{
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UINTN Base;
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UART_ACCESS_MODE AccessMode;
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Base = FindSerialIoBar (UartNumber + PchSerialIoIndexUart0, 0);
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//
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// Sanity checks to avoid infinite loop when trying to print through uninitialized UART
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//
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if ((Base & 0xFFFFFF00) == 0x0 || (Base & 0xFFFFF000) == 0xFFFFF000) {
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return 0;
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}
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EnablePciMse (UartNumber);
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AccessMode = DetectAccessMode (Base);
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//
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// Read the serial port status
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//
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if ((ReadRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_LSR) & B_PCH_SERIAL_IO_UART_LSR_RXDA) != 0) {
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return TRUE;
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}
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return FALSE;
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}
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