/** @file
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PCH Serial IO Lib implementation.
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All function in this library is available for PEI, DXE, and SMM,
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But do not support UEFI RUNTIME environment call.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <SaAccess.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/BaseLib.h>
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#include <IndustryStandard/Pci30.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/PcdLib.h>
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#include <Private/Library/GpioPrivateLib.h>
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#include <Library/PchSerialIoLib.h>
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#include <Library/PchSerialIoUartLib.h>
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#include <Include/PcieRegs.h>
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#include <Private/Library/PchPsfPrivateLib.h>
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#include <PchLimits.h>
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#include <Register/PchRegs.h>
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#include <Register/PchRegsPcr.h>
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#include <Register/PchRegsSerialIo.h>
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#define PCIEX_BAR_ADDR_MASK 0x0000007FFC000000
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typedef struct {
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UINT32 Bar0;
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UINT32 Bar1;
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} SERIAL_IO_CONTROLLER_DESCRIPTOR;
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GLOBAL_REMOVE_IF_UNREFERENCED SERIAL_IO_CONTROLLER_DESCRIPTOR mSerialIoAcpiAddress [PCH_MAX_SERIALIO_CONTROLLERS] =
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{
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{PCH_SERIAL_IO_BASE_ADDRESS + 0x0000, PCH_SERIAL_IO_BASE_ADDRESS + 0x1000},
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{PCH_SERIAL_IO_BASE_ADDRESS + 0x2000, PCH_SERIAL_IO_BASE_ADDRESS + 0x3000},
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{PCH_SERIAL_IO_BASE_ADDRESS + 0x4000, PCH_SERIAL_IO_BASE_ADDRESS + 0x5000},
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{PCH_SERIAL_IO_BASE_ADDRESS + 0x6000, PCH_SERIAL_IO_BASE_ADDRESS + 0x7000},
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{PCH_SERIAL_IO_BASE_ADDRESS + 0x8000, PCH_SERIAL_IO_BASE_ADDRESS + 0x9000},
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{PCH_SERIAL_IO_BASE_ADDRESS + 0xA000, PCH_SERIAL_IO_BASE_ADDRESS + 0xB000},
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{PCH_SERIAL_IO_BASE_ADDRESS + 0xC000, PCH_SERIAL_IO_BASE_ADDRESS + 0xD000},
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{PCH_SERIAL_IO_BASE_ADDRESS + 0xE000, PCH_SERIAL_IO_BASE_ADDRESS + 0xF000},
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{PCH_SERIAL_IO_BASE_ADDRESS + 0x10000, PCH_SERIAL_IO_BASE_ADDRESS + 0x11000},
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{PCH_SERIAL_IO_BASE_ADDRESS + 0x12000, PCH_SERIAL_IO_BASE_ADDRESS + 0x13000},
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{PCH_SERIAL_IO_BASE_ADDRESS + 0x14000, PCH_SERIAL_IO_BASE_ADDRESS + 0x15000},
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{PCH_SERIAL_IO_BASE_ADDRESS + 0x16000, PCH_SERIAL_IO_BASE_ADDRESS + 0x17000}
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};
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GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchSerialIoPciCfgCtrAddr [PCH_MAX_SERIALIO_CONTROLLERS] =
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{
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R_SERIAL_IO_PCR_PCICFGCTRL1,
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R_SERIAL_IO_PCR_PCICFGCTRL2,
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R_SERIAL_IO_PCR_PCICFGCTRL3,
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R_SERIAL_IO_PCR_PCICFGCTRL4,
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R_SERIAL_IO_PCR_PCICFGCTRL5,
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R_SERIAL_IO_PCR_PCICFGCTRL6,
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R_SERIAL_IO_PCR_PCICFGCTRL13,
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R_SERIAL_IO_PCR_PCICFGCTRL14,
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R_SERIAL_IO_PCR_PCICFGCTRL9,
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R_SERIAL_IO_PCR_PCICFGCTRL10,
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R_SERIAL_IO_PCR_PCICFGCTRL11
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};
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/**
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Returns Serial IO Controller Type I2C, SPI or UART
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@param[in] Number Number of SerialIo controller
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@retval I2C, SPI or UART
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@retval UNKNOWN - in case if undefined controller
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**/
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PCH_SERIAL_IO_CONTROLLER_TYPE
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GetSerialIoControllerType (
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IN PCH_SERIAL_IO_CONTROLLER Controller
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)
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{
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if (Controller >= PchSerialIoIndexI2C0 && Controller <= GetMaxI2cNumber ()) {
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return SERIAL_IO_I2C;
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} else if (Controller >= PchSerialIoIndexSpi0 && Controller < (PchSerialIoIndexSpi0 + GetPchMaxSerialIoSpiControllersNum ())) {
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return SERIAL_IO_SPI;
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} else if (Controller >= PchSerialIoIndexUart0 && Controller <= PchSerialIoIndexUart2) {
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return SERIAL_IO_UART;
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}
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return SERIAL_IO_UNKNOWN;
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}
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/**
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Checks if given Serial IO Controller Function equals 0
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@param[in] SerialIoNumber Serial IO device
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@retval TRUE if SerialIO Function is equal to 0
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FALSE if Function is higher then 0
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**/
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BOOLEAN
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IsSerialIoFunctionZero (
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IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber
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)
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{
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if (GetSerialIoFunctionNumber (SerialIoNumber) > 0) {
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return FALSE;
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}
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return TRUE;
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}
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/**
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Checks if given Serial IO Controller is enabled or not
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@param[in] DeviceNumber device number
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@param[in] FunctionNumber function number
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@retval TRUE TRUE if given serial io device is enabled.
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@retval FALSE FALSE if given serial io device is disabled.
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**/
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BOOLEAN
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IsSerialIoDeviceEnabled (
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IN UINT8 DeviceNumber,
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IN UINT8 FunctionNumber
|
)
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{
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if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (DEFAULT_PCI_SEGMENT_NUMBER_PCH, DEFAULT_PCI_BUS_NUMBER_PCH, DeviceNumber, FunctionNumber, PCI_DEVICE_ID_OFFSET)) != 0xFFFF) {
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return TRUE;
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}
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return FALSE;
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}
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/**
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Checks if given device corresponds to any of LPSS Devices
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@param[in] DeviceNumber device number
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@param[in] FunctionNumber function number
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@retval TRUE if SerialIO Device/Function Number is equal to any of LPSS devices
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FALSE Device/Function is not in Serial IO scope
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**/
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BOOLEAN
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IsSerialIoDevice (
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IN UINT8 DeviceNumber,
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IN UINT8 FunctionNumber
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)
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{
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PCH_SERIAL_IO_CONTROLLER Controller;
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PCH_SERIAL_IO_CONTROLLER ControllerMax;
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ControllerMax = GetPchMaxSerialIoControllersNum ();
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for (Controller = 0; Controller < ControllerMax; Controller++) {
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if ((DeviceNumber == GetSerialIoDeviceNumber (Controller)) &&
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(FunctionNumber == GetSerialIoFunctionNumber (Controller))) {
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return TRUE;
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}
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}
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return FALSE;
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}
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/**
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Gets Pci Config control offset
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@param[in] DeviceNumber device number
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@param[in] FunctionNumber function number
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@retval CfgCtrAddr Offset of Pci config control
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0 if Device and Function do not correspond to Serial IO
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**/
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UINT16
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GetSerialIoConfigControlOffset (
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IN UINT8 DeviceNumber,
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IN UINT8 FunctionNumber
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)
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{
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PCH_SERIAL_IO_CONTROLLER Controller;
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PCH_SERIAL_IO_CONTROLLER ControllerMax;
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ControllerMax = GetPchMaxSerialIoControllersNum ();
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for (Controller = 0; Controller < ControllerMax; Controller++) {
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if ((DeviceNumber == GetSerialIoDeviceNumber (Controller)) &&
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(FunctionNumber == GetSerialIoFunctionNumber (Controller))) {
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return mPchSerialIoPciCfgCtrAddr[Controller];
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}
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}
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return 0;
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}
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/**
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Checks if Device with given AcpiHid string is one of SerialIo controllers
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If yes, its number is returned through Number parameter, otherwise Number is not updated
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@param[in] AcpiHid String
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@param[out] Number Number of SerialIo controller
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@retval TRUE yes it is a SerialIo controller
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@retval FALSE no it isn't a SerialIo controller
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**/
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BOOLEAN
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IsSerialIoAcpiHid (
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IN CHAR8 *AcpiHid,
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OUT PCH_SERIAL_IO_CONTROLLER *Number
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)
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{
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PCH_SERIAL_IO_CONTROLLER Controller;
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PCH_SERIAL_IO_CONTROLLER ControllerMax;
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ControllerMax = GetPchMaxSerialIoControllersNum ();
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for (Controller = 0; Controller < ControllerMax; Controller++) {
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if (!AsciiStrCmp ((const CHAR8 *) AcpiHid, GetSerialIoAcpiHid(Controller))) {
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*Number = Controller;
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return TRUE;
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}
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}
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return FALSE;
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}
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/**
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Finds BAR values of SerialIo devices.
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SerialIo devices can be configured to not appear on PCI so traditional method of reading BAR might not work.
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If the SerialIo device is in PCI mode, a request for BAR1 will return its PCI CFG space instead
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@param[in] SerialIoDevice Serial IO device
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@param[in] BarNumber 0=BAR0, 1=BAR1
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@retval SerialIo Bar value
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**/
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UINTN
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FindSerialIoBar (
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IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice,
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IN UINT8 BarNumber
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)
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{
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UINT64 Bar;
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UINT64 PcieBase;
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UINT64 PciSegBase;
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UINT16 VenId;
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UINT32 Device;
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UINT32 Function;
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Device = GetSerialIoDeviceNumber (SerialIoDevice);
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Function = GetSerialIoFunctionNumber (SerialIoDevice);
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PcieBase = PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PCIEXBAR)); // S0:B0:D0:F0:R60
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PcieBase = (PcieBase & PCIEX_BAR_ADDR_MASK) + LShiftU64 (DEFAULT_PCI_BUS_NUMBER_PCH, 20) + LShiftU64 (Device, 15) + LShiftU64 (Function, 12);
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PciSegBase = PCI_SEGMENT_LIB_ADDRESS (
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DEFAULT_PCI_SEGMENT_NUMBER_PCH,
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DEFAULT_PCI_BUS_NUMBER_PCH,
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Device,
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Function,
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0
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);
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VenId = PciSegmentRead16 (PciSegBase + PCI_VENDOR_ID_OFFSET) & 0xFFFF;
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if (VenId == V_PCH_INTEL_VENDOR_ID) {
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if (BarNumber == 1) {
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return ((UINTN) PcieBase);
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}
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Bar = PciSegmentRead32 (PciSegBase + PCI_BASE_ADDRESSREG_OFFSET);
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// For 64-Bit Memory Space BARs ((BAR[x] & 0xFFFFFFF0) + ((BAR[x+1] & 0xFFFFFFFF) << 32)
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if ((Bar & B_PCI_BAR_MEMORY_TYPE_MASK) == B_PCI_BAR_MEMORY_TYPE_64) {
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Bar = (Bar & 0xFFFFF000) + (UINTN) ((UINT64) LShiftU64 ((PciSegmentRead32 (PciSegBase + PCI_BASE_ADDRESSREG_OFFSET + 4) & 0xFFFFFFFF), 32));
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return (UINTN) Bar;
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}
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return (UINTN) (Bar & 0xFFFFF000);
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}
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//PCI mode failed? Try hardcoded addresses from ACPI
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if (BarNumber == 0) {
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Bar = mSerialIoAcpiAddress[SerialIoDevice].Bar0;
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} else {
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Bar = mSerialIoAcpiAddress[SerialIoDevice].Bar1;
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}
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return (UINTN) Bar;
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}
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/**
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Get PSF_PORT for a given Serial IO Controller
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@param[in] Controller Serial IO controller number
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**/
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STATIC
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PSF_PORT
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SerialIoPsfPort (
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IN PCH_SERIAL_IO_CONTROLLER Controller
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)
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{
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switch (GetSerialIoControllerType (Controller)) {
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case SERIAL_IO_I2C:
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return PsfSerialIoI2cPort (Controller - PchSerialIoIndexI2C0);
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case SERIAL_IO_SPI:
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return PsfSerialIoSpiPort (Controller - PchSerialIoIndexSpi0);
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case SERIAL_IO_UART:
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return PsfSerialIoUartPort (Controller - PchSerialIoIndexUart0);
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case SERIAL_IO_UNKNOWN:
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default:
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return (PSF_PORT){0};
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}
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}
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/**
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Configures Serial IO Controller
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@param[in] Controller Serial IO controller number
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@param[in] DeviceMode Device operation mode
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@param[in] PsfDisable Disable device at PSF level
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@retval None
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**/
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VOID
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ConfigureSerialIoController (
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IN PCH_SERIAL_IO_CONTROLLER Controller,
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IN PCH_SERIAL_IO_MODE DeviceMode,
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IN BOOLEAN PsfDisable
|
)
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{
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UINT64 PciCfgBase;
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UINT32 Data32And;
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UINT32 Data32Or;
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UINT16 *SerialIoPciCfgCtrAddr;
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UINT8 Uart8BitLoop;
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/*
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Please do not add DEBUG message here because this routine is configuring SerialIoUart.
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Printing DEBUG message before SerialIoUart initialization may cause system hang (in Debug build).
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*/
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//
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// This is to prevent from overflow of array access.
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//
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if (Controller >= PCH_MAX_SERIALIO_CONTROLLERS) {
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return;
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}
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if (GetSerialIoControllerType (Controller) == SERIAL_IO_UNKNOWN) {
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return;
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}
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PciCfgBase = PCI_SEGMENT_LIB_ADDRESS (
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DEFAULT_PCI_SEGMENT_NUMBER_PCH,
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DEFAULT_PCI_BUS_NUMBER_PCH,
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GetSerialIoDeviceNumber (Controller),
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GetSerialIoFunctionNumber (Controller),
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0
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);
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//
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// Do not modify a device that has already been disabled/hidden
|
//
|
if (PciSegmentRead16 (PciCfgBase + PCI_VENDOR_ID_OFFSET) != V_PCH_INTEL_VENDOR_ID) {
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return;
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}
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///
|
/// Step 0. set Bit 16,17,18.
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///
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PciSegmentOr32 (PciCfgBase + R_SERIAL_IO_CFG_D0I3MAXDEVPG, BIT18 | BIT17 | BIT16);
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|
SerialIoPciCfgCtrAddr = mPchSerialIoPciCfgCtrAddr;
|
|
switch (DeviceMode) {
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case PchSerialIoDisabled:
|
///
|
/// Step 1. Put device in D3
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/// Step 2. Function Disable in PSF
|
///
|
PciSegmentOr32 (PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, BIT1 | BIT0);
|
|
if (PsfDisable) {
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PsfDisableDevice (SerialIoPsfPort (Controller));
|
}
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break;
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case PchSerialIoAcpi:
|
case PchSerialIoHidden:
|
///
|
/// reenable BAR1 in case it was disabled earlier
|
/// Read back is needed to enforce the sideband and primary ordering.
|
///
|
PchPcrAndThenOr32WithReadback (
|
PID_SERIALIO,
|
SerialIoPciCfgCtrAddr[Controller],
|
(UINT32) ~(B_SERIAL_IO_PCR_PCICFGCTRL_BAR1_DIS),
|
0
|
);
|
PsfEnableDeviceBar (SerialIoPsfPort (Controller), BIT3 | BIT2);
|
///
|
/// Step 1. Assign BAR0
|
/// Step 2. Assign BAR1
|
///
|
PciSegmentWrite32 (PciCfgBase + R_SERIAL_IO_CFG_BAR0_LOW, mSerialIoAcpiAddress[Controller].Bar0);
|
PciSegmentWrite32 (PciCfgBase + R_SERIAL_IO_CFG_BAR0_HIGH, 0x0);
|
PciSegmentWrite32 (PciCfgBase + R_SERIAL_IO_CFG_BAR1_LOW, mSerialIoAcpiAddress[Controller].Bar1);
|
PciSegmentWrite32 (PciCfgBase + R_SERIAL_IO_CFG_BAR1_HIGH, 0x0);
|
///
|
/// Step 3. Set Memory space Enable
|
///
|
PciSegmentOr32 (PciCfgBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
|
///
|
/// Step 4. Disable device's PciCfg and enable ACPI interrupts
|
/// Read back is needed to enforce the sideband and primary ordering.
|
///
|
PchPcrAndThenOr32WithReadback (
|
PID_SERIALIO,
|
SerialIoPciCfgCtrAddr[Controller],
|
~0u,
|
(B_SERIAL_IO_PCR_PCICFGCTRL_PCI_CFG_DIS | B_SERIAL_IO_PCR_PCICFGCTRL_ACPI_INTR_EN)
|
);
|
///
|
/// Step 5. Disable device's PciCfg in PSF
|
///
|
PsfHideDevice (SerialIoPsfPort (Controller));
|
///
|
/// get controller out of reset
|
///
|
MmioOr32 (
|
mSerialIoAcpiAddress[Controller].Bar0 + R_SERIAL_IO_MEM_PPR_RESETS,
|
B_SERIAL_IO_MEM_PPR_RESETS_FUNC | B_SERIAL_IO_MEM_PPR_RESETS_APB | B_SERIAL_IO_MEM_PPR_RESETS_IDMA
|
);
|
break;
|
case PchSerialIoPci:
|
//
|
// Check If device is already initialized
|
//
|
if (PciSegmentRead32 (PciCfgBase + PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000) {
|
return;
|
}
|
///
|
/// reenable PciCfg in case it was disabled earlier
|
/// Read back is needed to enforce the sideband and primary ordering.
|
///
|
PchPcrAndThenOr32WithReadback (
|
PID_SERIALIO,
|
SerialIoPciCfgCtrAddr[Controller],
|
(UINT32) ~(B_SERIAL_IO_PCR_PCICFGCTRL_PCI_CFG_DIS | B_SERIAL_IO_PCR_PCICFGCTRL_ACPI_INTR_EN),
|
0
|
);
|
PsfUnhideDevice (SerialIoPsfPort (Controller));
|
///
|
/// Disable Bar1
|
/// Disable Bar1 in PSF
|
/// Read back is needed to enforce the sideband and primary ordering.
|
///
|
PchPcrAndThenOr32WithReadback (
|
PID_SERIALIO,
|
SerialIoPciCfgCtrAddr[Controller],
|
~0u,
|
B_SERIAL_IO_PCR_PCICFGCTRL_BAR1_DIS
|
);
|
PsfDisableDeviceBar (SerialIoPsfPort (Controller), BIT3 | BIT2);
|
|
//
|
// Assign BAR0 and Set Memory space Enable
|
//
|
PciSegmentWrite32 (PciCfgBase + R_SERIAL_IO_CFG_BAR0_LOW, mSerialIoAcpiAddress[Controller].Bar0);
|
PciSegmentWrite32 (PciCfgBase + R_SERIAL_IO_CFG_BAR0_HIGH, 0x0);
|
PciSegmentOr32 (PciCfgBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
|
///
|
/// get controller out of reset
|
///
|
MmioOr32 (
|
mSerialIoAcpiAddress[Controller].Bar0 + R_SERIAL_IO_MEM_PPR_RESETS,
|
B_SERIAL_IO_MEM_PPR_RESETS_FUNC | B_SERIAL_IO_MEM_PPR_RESETS_APB | B_SERIAL_IO_MEM_PPR_RESETS_IDMA
|
);
|
break;
|
default:
|
return;
|
}
|
|
///
|
/// Step X. Program clock dividers for UARTs
|
/// Step Y. Enable Byte addressing for UARTs in legacy mode
|
///
|
if ((Controller >= PchSerialIoIndexUart0 && Controller <= PchSerialIoIndexUart2) && (DeviceMode != PchSerialIoDisabled)) {
|
MmioWrite32 (mSerialIoAcpiAddress[Controller].Bar0 + R_SERIAL_IO_MEM_PPR_CLK,
|
(B_SERIAL_IO_MEM_PPR_CLK_UPDATE | (V_SERIAL_IO_MEM_PPR_CLK_N_DIV << 16) |
|
(V_SERIAL_IO_MEM_PPR_CLK_M_DIV << 1) | B_SERIAL_IO_MEM_PPR_CLK_EN )
|
);
|
|
Data32And = (UINT32) (~(B_SERIAL_IO_PCR_GPPRVRW7_UART0_BYTE_ADDR_EN << (Controller - PchSerialIoIndexUart0)));
|
Data32Or = 0x0;
|
if (DeviceMode == PchSerialIoHidden) {
|
Data32Or = (B_SERIAL_IO_PCR_GPPRVRW7_UART0_BYTE_ADDR_EN << (Controller - PchSerialIoIndexUart0));
|
}
|
PchPcrAndThenOr32 (PID_SERIALIO, R_SERIAL_IO_PCR_GPPRVRW7,Data32And,Data32Or);
|
//
|
// Dummy read after setting any of GPPRVRW7.
|
// Required for UART 16550 8-bit Legacy mode to become active
|
//
|
MmioRead32 (mSerialIoAcpiAddress[Controller].Bar0 + R_SERIAL_IO_MEM_PPR_CLK);
|
//
|
// Loop until Uart has successfuly moved to 8 bit mode
|
//
|
if (DeviceMode == PchSerialIoHidden) {
|
Uart8BitLoop = 10;
|
while (Uart8BitLoop > 0) {
|
if (DetectAccessMode (mSerialIoAcpiAddress[Controller].Bar0) == AccessMode8bit) {
|
return;
|
}
|
Uart8BitLoop--;
|
}
|
}
|
}
|
|
///
|
/// Step Z. Program I2C SDA hold registers
|
///
|
if (Controller >= PchSerialIoIndexI2C0 && Controller <= GetMaxI2cNumber ()) {
|
if (DeviceMode != PchSerialIoDisabled) {
|
MmioOr32 (mSerialIoAcpiAddress[Controller].Bar0 + R_SERIAL_IO_MEM_I2C_SDA_HOLD, V_SERIAL_IO_MEM_I2C_SDA_HOLD_VALUE);
|
}
|
}
|
|
}
|
|
