/** @file
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PCH PCIE root port library.
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All function in this library is available for PEI, DXE, and SMM,
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But do not support UEFI RUNTIME environment call.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchPcieRpLib.h>
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#include <PcieRegs.h>
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#include <Register/PchRegs.h>
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#include <Register/PchRegsPcie.h>
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#include <Register/PchRegsPcr.h>
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GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_PCIE_CONTROLLER_INFO mPchPcieControllerInfo[] = {
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{ PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, PID_SPA, 0 },
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{ PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, PID_SPB, 4 },
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{ PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, PID_SPC, 8 },
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{ PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, PID_SPD, 12 },
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{ PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, PID_SPE, 16 }, // PCH-H only
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{ PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, PID_SPF, 20 } // PCH-H only
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};
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GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 mPchPcieControllerInfoSize = sizeof (mPchPcieControllerInfo) / sizeof (mPchPcieControllerInfo[0]);
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPchLpRstPcieStorageSupportedPort[] = {
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RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, // RP1..RP4
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RST_PCIE_STORAGE_CR_1, RST_PCIE_STORAGE_CR_1, RST_PCIE_STORAGE_CR_1, RST_PCIE_STORAGE_CR_1, // RP5..RP8
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RST_PCIE_STORAGE_CR_2, RST_PCIE_STORAGE_CR_2, RST_PCIE_STORAGE_CR_2, RST_PCIE_STORAGE_CR_2, // RP9..RP12
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RST_PCIE_STORAGE_CR_3, RST_PCIE_STORAGE_CR_3, RST_PCIE_STORAGE_CR_3, RST_PCIE_STORAGE_CR_3 // RP13..RP16
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};
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPchHRstPcieStorageSupportedPort[] = {
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RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, // RP1..RP4
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RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, // RP5..RP8
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RST_PCIE_STORAGE_CR_1, RST_PCIE_STORAGE_CR_1, RST_PCIE_STORAGE_CR_1, RST_PCIE_STORAGE_CR_1, // RP9..RP12
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RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, // RP13..RP16
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RST_PCIE_STORAGE_CR_3, RST_PCIE_STORAGE_CR_3, RST_PCIE_STORAGE_CR_3, RST_PCIE_STORAGE_CR_3, // RP17..RP20
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RST_PCIE_STORAGE_CR_2, RST_PCIE_STORAGE_CR_2, RST_PCIE_STORAGE_CR_2, RST_PCIE_STORAGE_CR_2 // RP21..RP24
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};
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/**
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Get Pch Pcie Root Port Device and Function Number by Root Port physical Number
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@param[in] RpNumber Root port physical number. (0-based)
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@param[out] RpDev Return corresponding root port device number.
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@param[out] RpFun Return corresponding root port function number.
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@retval EFI_SUCCESS Root port device and function is retrieved
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@retval EFI_INVALID_PARAMETER RpNumber is invalid
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**/
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EFI_STATUS
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EFIAPI
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GetPchPcieRpDevFun (
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IN UINTN RpNumber,
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OUT UINTN *RpDev,
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OUT UINTN *RpFun
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)
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{
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UINTN Index;
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UINTN FuncIndex;
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UINT32 PciePcd;
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if (RpNumber >= GetPchMaxPciePortNum ()) {
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DEBUG ((DEBUG_ERROR, "GetPchPcieRpDevFun invalid RpNumber %x", RpNumber));
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ASSERT (FALSE);
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return EFI_INVALID_PARAMETER;
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}
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Index = RpNumber / PCH_PCIE_CONTROLLER_PORTS;
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FuncIndex = RpNumber - mPchPcieControllerInfo[Index].RpNumBase;
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*RpDev = mPchPcieControllerInfo[Index].DevNum;
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PciePcd = PchPcrRead32 (mPchPcieControllerInfo[Index].Pid, R_SPX_PCR_PCD);
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*RpFun = (PciePcd >> (FuncIndex * S_SPX_PCR_PCD_RP_FIELD)) & B_SPX_PCR_PCD_RP1FN;
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return EFI_SUCCESS;
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}
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/**
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Get Root Port physical Number by Pch Pcie Root Port Device and Function Number
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@param[in] RpDev Root port device number.
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@param[in] RpFun Root port function number.
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@param[out] RpNumber Return corresponding physical Root Port index (0-based)
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@retval EFI_SUCCESS Physical root port is retrieved
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**/
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EFI_STATUS
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EFIAPI
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GetPchPcieRpNumber (
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IN UINTN RpDev,
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IN UINTN RpFun,
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OUT UINTN *RpNumber
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)
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{
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UINT64 RpBase;
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RpBase = PCI_SEGMENT_LIB_ADDRESS (DEFAULT_PCI_SEGMENT_NUMBER_PCH, DEFAULT_PCI_BUS_NUMBER_PCH, RpDev, RpFun, 0);
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*RpNumber = (PciSegmentRead32 (RpBase + R_PCH_PCIE_CFG_LCAP) >> N_PCH_PCIE_CFG_LCAP_PN) -1;
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return EFI_SUCCESS;
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}
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/**
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Gets pci segment base address of PCIe root port.
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@param RpIndex Root Port Index (0 based)
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@return PCIe port base address.
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**/
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UINT64
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PchPcieBase (
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IN UINT32 RpIndex
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)
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{
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UINTN RpDevice;
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UINTN RpFunction;
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GetPchPcieRpDevFun (RpIndex, &RpDevice, &RpFunction);
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return PCI_SEGMENT_LIB_ADDRESS (DEFAULT_PCI_SEGMENT_NUMBER_PCH, DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction, 0);
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}
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/**
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Determines whether L0s is supported on current stepping.
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@return TRUE if L0s is supported, FALSE otherwise
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**/
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BOOLEAN
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PchIsPcieL0sSupported (
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VOID
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)
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{
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return TRUE;
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}
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/**
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Some early PCH steppings require Native ASPM to be disabled due to hardware issues:
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- RxL0s exit causes recovery
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- Disabling PCIe L0s capability disables L1
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Use this function to determine affected steppings.
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@return TRUE if Native ASPM is supported, FALSE otherwise
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**/
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BOOLEAN
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PchIsPcieNativeAspmSupported (
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VOID
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)
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{
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return PchIsPcieL0sSupported ();
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}
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/**
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Check the RST PCIe Storage Cycle Router number according to the root port number and PCH type
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@param[in] RootPortNum Root Port Number
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@return The RST PCIe Storage Cycle Router Number
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**/
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UINT8
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RstGetCycleRouterNumber (
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IN UINT32 RootPortNum
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)
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{
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if (IsPchLp ()) {
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if (RootPortNum < ARRAY_SIZE (mPchLpRstPcieStorageSupportedPort)) {
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return mPchLpRstPcieStorageSupportedPort[RootPortNum];
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}
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} else if (IsPchH ()) {
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if (RootPortNum < ARRAY_SIZE (mPchHRstPcieStorageSupportedPort)) {
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return mPchHRstPcieStorageSupportedPort[RootPortNum];
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}
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}
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return RST_PCIE_STORAGE_CR_INVALID;
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}
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