/** @file
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Register definition for PSTH component
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Conventions:
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- Register definition format:
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Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
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- Prefix:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register size
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Definitions beginning with "N_" are the bit position
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- [GenerationName]:
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Three letter acronym of the generation is used .
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Register name without GenerationName applies to all generations.
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- [ComponentName]:
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This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
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Register name without ComponentName applies to all components.
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Register that is specific to -H denoted by "_PCH_H_" in component name.
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Register that is specific to -LP denoted by "_PCH_LP_" in component name.
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- SubsystemName:
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This field indicates the subsystem name of the component that the register belongs to
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(e.g. PCIE, USB, SATA, GPIO, PMC etc.).
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- RegisterSpace:
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MEM - MMIO space register of subsystem.
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IO - IO space register of subsystem.
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PCR - Private configuration register of subsystem.
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CFG - PCI configuration space register of subsystem.
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- RegisterName:
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Full register name.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_PSTH_H_
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#define _PCH_REGS_PSTH_H_
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//
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// Private chipset register (Memory space) offset definition
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// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well.
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//
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//
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// PSTH and IO Trap PCRs (PID:PSTH)
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//
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#define R_PSTH_PCR_PSTHCTL 0x1D00 ///< PSTH control register
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#define B_PSTH_PCR_PSTHIOSFPTCGE BIT2 ///< PSTH IOSF primary trunk clock gating enable
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#define B_PSTH_PCR_PSTHIOSFSTCGE BIT1 ///< PSTH IOSF sideband trunk clock gating enable
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#define B_PSTH_PCR_PSTHDCGE BIT0 ///< PSTH dynamic clock gating enable
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#define R_PSTH_PCR_TRPST 0x1E00 ///< Trap status register
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#define B_PSTH_PCR_TRPST_CTSS 0x0000000F ///< Cycle Trap SMI# Status mask
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#define R_PSTH_PCR_TRPC 0x1E10 ///< Trapped cycle
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#define B_PSTH_PCR_TRPC_RW BIT24 ///< Read/Write#: 1=Read, 0=Write
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#define B_PSTH_PCR_TRPC_AHBE 0x00000000000F0000 ///< Active high byte enables
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#define B_PSTH_PCR_TRPC_IOA 0x000000000000FFFC ///< Trap cycle I/O address
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#define R_PSTH_PCR_TRPD 0x1E18 ///< Trapped write data
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#define B_PSTH_PCR_TRPD_IOD 0x00000000FFFFFFFF ///< Trap cycle I/O data
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#define R_PSTH_PCR_TRPREG0 0x1E80 ///< IO Tarp 0 register
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#define R_PSTH_PCR_TRPREG1 0x1E88 ///< IO Tarp 1 register
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#define R_PSTH_PCR_TRPREG2 0x1E90 ///< IO Tarp 2 register
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#define R_PSTH_PCR_TRPREG3 0x1E98 ///< IO Tarp 3 register
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#define B_PSTH_PCR_TRPREG_RWM BIT17 ///< 49 - 32 for 32 bit access, Read/Write mask
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#define B_PSTH_PCR_TRPREG_RWIO BIT16 ///< 48 - 32 for 32 bit access, Read/Write#, 1=Read, 0=Write
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#define N_PSTH_PCR_TRPREG_RWIO 16 ///< 48 - 32 for 32 bit access, 16bit shift for Read/Write field
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#define N_PSTH_PCR_TRPREG_BEM 36
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#define B_PSTH_PCR_TRPREG_BEM 0x000000F000000000 ///< Byte enable mask
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#define N_PSTH_PCR_TRPREG_BE 32
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#define B_PSTH_PCR_TRPREG_BE 0x0000000F00000000 ///< Byte enable
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#define B_PSTH_PCR_TRPREG_AM 0x0000000000FC0000 ///< IO Address mask
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#define B_PSTH_PCR_TRPREG_AD 0x000000000000FFFC ///< IO Address
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#define B_PSTH_PCR_TRPREG_TSE BIT0 ///< Trap and SMI# Enable
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#endif
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