/** @file
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Register definition for PSF component
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Conventions:
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- Register definition format:
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Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
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- Prefix:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register size
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Definitions beginning with "N_" are the bit position
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- [GenerationName]:
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Three letter acronym of the generation is used .
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Register name without GenerationName applies to all generations.
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- [ComponentName]:
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This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
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Register name without ComponentName applies to all components.
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Register that is specific to -H denoted by "_PCH_H_" in component name.
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Register that is specific to -LP denoted by "_PCH_LP_" in component name.
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- SubsystemName:
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This field indicates the subsystem name of the component that the register belongs to
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(e.g. PCIE, USB, SATA, GPIO, PMC etc.).
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- RegisterSpace:
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MEM - MMIO space register of subsystem.
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IO - IO space register of subsystem.
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PCR - Private configuration register of subsystem.
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CFG - PCI configuration space register of subsystem.
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- RegisterName:
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Full register name.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_PSF_H_
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#define _PCH_REGS_PSF_H_
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//
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// Private chipset register (Memory space) offset definition
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// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well.
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//
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//
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// PSFx segment registers
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//
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#define R_PCH_PSF_PCR_GLOBAL_CONFIG 0x4000 ///< PSF Segment Global Configuration Register
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#define B_PCH_PSF_PCR_ROOTSPACE_CONFIG_RSX_ENADDRP2P BIT1
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#define B_PCH_PSF_PCR_ROOTSPACE_CONFIG_RSX_VTDEN BIT0
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#define S_PCH_PSFX_PCR_DEV_GNTCNT_RELOAD_DGCR 4
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#define S_PCH_PSFX_PCR_TARGET_GNTCNT_RELOAD 4
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#define B_PCH_PSFX_PCR_DEV_GNTCNT_RELOAD_DGCR_GNT_CNT_RELOAD 0x1F
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#define B_PCH_PSFX_PCR_TARGET_GNTCNT_RELOAD_GNT_CNT_RELOAD 0x1F
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#define N_PCH_PSFX_PCR_MC_CONTROL_MCASTX_NUMMC 1
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#define B_PCH_PSFX_PCR_MC_CONTROL_MCASTX_MULTCEN BIT0
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//
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// PSFx PCRs definitions
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//
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#define R_PCH_PSFX_PCR_T0_SHDW_BAR0 0 ///< PCI BAR0
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#define R_PCH_PSFX_PCR_T0_SHDW_BAR1 0x04 ///< PCI BAR1
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#define R_PCH_PSFX_PCR_T0_SHDW_BAR2 0x08 ///< PCI BAR2
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#define R_PCH_PSFX_PCR_T0_SHDW_BAR3 0x0C ///< PCI BAR3
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#define R_PCH_PSFX_PCR_T0_SHDW_BAR4 0x10 ///< PCI BAR4
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#define R_PCH_PSFX_PCR_T0_SHDW_PCIEN 0x1C ///< PCI configuration space enable bits
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#define N_PCH_PSFX_PCR_T0_SHDW_PCIEN_BARXDIS 16
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#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR0DIS BIT16 ///< Disable BAR0
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#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR1DIS BIT17 ///< Disable BAR1
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#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR2DIS BIT18 ///< Disable BAR2
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#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR3DIS BIT19 ///< Disable BAR3
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#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR4DIS BIT20 ///< Disable BAR4
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#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR5DIS BIT21 ///< Disable BAR5
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#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS BIT8 ///< Function disable
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#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_MEMEN BIT1 ///< Memory decoding enable
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#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_IOEN BIT0 ///< IO decoding enable
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#define R_PCH_PSFX_PCR_T0_SHDW_PMCSR 0x20 ///< PCI power management configuration
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#define B_PCH_PSFX_PCR_T0_SHDW_PMCSR_PWRST (BIT1 | BIT0) ///< Power status
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#define R_PCH_PSFX_PCR_T0_SHDW_CFG_DIS 0x38 ///< PCI configuration disable
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#define B_PCH_PSFX_PCR_T0_SHDW_CFG_DIS_CFGDIS BIT0 ///< config disable
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#define R_PCH_PSFX_PCR_T1_SHDW_PCIEN 0x3C ///< PCI configuration space enable bits
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#define B_PCH_PSFX_PCR_T1_SHDW_PCIEN_FUNDIS BIT8 ///< Function disable
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#define B_PCH_PSFX_PCR_T1_SHDW_PCIEN_MEMEN BIT1 ///< Memory decoding enable
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#define B_PCH_PSFX_PCR_T1_SHDW_PCIEN_IOEN BIT0 ///< IO decoding enable
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#define B_PCH_PSFX_PCR_TX_AGENT_FUNCTION_CONFIG_DEVICE 0x01F0 ///< device number
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#define N_PCH_PSFX_PCR_TX_AGENT_FUNCTION_CONFIG_DEVICE 4
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#define B_PCH_PSFX_PCR_TX_AGENT_FUNCTION_CONFIG_FUNCTION (BIT3 | BIT2 | BIT1) ///< function number
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#define N_PCH_PSFX_PCR_TX_AGENT_FUNCTION_CONFIG_FUNCTION 1
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#define B_PCH_PSFX_PCR_TARGET_CHANNELID 0xFF
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#define B_PCH_PSFX_PCR_TARGET_PORTID 0x7F00
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#define N_PCH_PSFX_PCR_TARGET_PORTID 8
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#define B_PCH_PSFX_PCR_TARGET_PORTGROUPID BIT15
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#define N_PCH_PSFX_PCR_TARGET_PORTGROUPID 15
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#define B_PCH_PSFX_PCR_TARGET_PSFID 0xFF0000
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#define N_PCH_PSFX_PCR_TARGET_PSFID 16
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#define B_PCH_PSFX_PCR_TARGET_CHANMAP BIT31
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#endif
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