/** @file
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Register definition for FIA component
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Conventions:
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- Register definition format:
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Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
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- Prefix:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register size
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Definitions beginning with "N_" are the bit position
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- [GenerationName]:
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Three letter acronym of the generation is used .
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Register name without GenerationName applies to all generations.
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- [ComponentName]:
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This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
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Register name without ComponentName applies to all components.
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Register that is specific to -H denoted by "_PCH_H_" in component name.
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Register that is specific to -LP denoted by "_PCH_LP_" in component name.
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- SubsystemName:
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This field indicates the subsystem name of the component that the register belongs to
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(e.g. PCIE, USB, SATA, GPIO, PMC etc.).
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- RegisterSpace:
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MEM - MMIO space register of subsystem.
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IO - IO space register of subsystem.
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PCR - Private configuration register of subsystem.
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CFG - PCI configuration space register of subsystem.
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- RegisterName:
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Full register name.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_FIA_H_
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#define _PCH_REGS_FIA_H_
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//
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// Private chipset register (Memory space) offset definition
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// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well.
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//
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//
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// PCH FIA lane owner encoding
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//
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#define V_PCH_FIA_PCR_LANE_OWN_PCIEDMI 0x0
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#define V_PCH_FIA_PCR_LANE_OWN_USB3 0x1
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#define V_PCH_FIA_PCR_LANE_OWN_SATA 0x2
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#define V_PCH_FIA_PCR_LANE_OWN_GBE 0x3
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#define V_PCH_FIA_PCR_LANE_OWN_MOBEXP 0x4
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#define V_PCH_FIA_PCR_LANE_OWN_SSIC 0x5
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#define V_PCH_FIA_PCR_LANE_OWN_CSI3 0x6
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#define V_PCH_FIA_PCR_LANE_OWN_UFS 0x7
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#define B_PCH_FIA_PCR_L0O (BIT3 | BIT2 | BIT1 | BIT0)
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#define B_PCH_FIA_PCR_L1O (BIT7 | BIT6 | BIT5 | BIT4)
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#define B_PCH_FIA_PCR_L2O (BIT11 | BIT10 | BIT9 | BIT8)
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#define B_PCH_FIA_PCR_L3O (BIT15 | BIT14 | BIT13 | BIT12)
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#define B_PCH_FIA_PCR_L4O (BIT19 | BIT18 | BIT17 | BIT16)
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#define B_PCH_FIA_PCR_L5O (BIT23 | BIT22 | BIT21 | BIT20)
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#define B_PCH_FIA_PCR_L6O (BIT27 | BIT26 | BIT25 | BIT24)
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#define B_PCH_FIA_PCR_L7O (BIT31 | BIT30 | BIT29 | BIT28)
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#define B_PCH_FIA_PCR_L8O (BIT3 | BIT2 | BIT1 | BIT0)
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#define B_PCH_FIA_PCR_L9O (BIT7 | BIT6 | BIT5 | BIT4)
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#define B_PCH_FIA_PCR_L10O (BIT11 | BIT10 | BIT9 | BIT8)
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#define B_PCH_FIA_PCR_L11O (BIT15 | BIT14 | BIT13 | BIT12)
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#define B_PCH_FIA_PCR_L12O (BIT19 | BIT18 | BIT17 | BIT16)
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#define B_PCH_FIA_PCR_L13O (BIT23 | BIT22 | BIT21 | BIT20)
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#define B_PCH_FIA_PCR_L14O (BIT27 | BIT26 | BIT25 | BIT24)
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#define B_PCH_FIA_PCR_L15O (BIT31 | BIT30 | BIT29 | BIT28)
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#define B_PCH_FIA_PCR_L16O (BIT3 | BIT2 | BIT1 | BIT0)
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#define B_PCH_FIA_PCR_L17O (BIT7 | BIT6 | BIT5 | BIT4)
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#define B_PCH_FIA_PCR_L18O (BIT11 | BIT10 | BIT9 | BIT8)
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#define B_PCH_FIA_PCR_L19O (BIT15 | BIT14 | BIT13 | BIT12)
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#define B_PCH_FIA_PCR_L20O (BIT19 | BIT18 | BIT17 | BIT16)
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#define B_PCH_FIA_PCR_L21O (BIT23 | BIT22 | BIT21 | BIT20)
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#define B_PCH_FIA_PCR_L22O (BIT27 | BIT26 | BIT25 | BIT24)
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#define B_PCH_FIA_PCR_L23O (BIT31 | BIT30 | BIT29 | BIT28)
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#define B_PCH_FIA_PCR_L24O (BIT3 | BIT2 | BIT1 | BIT0)
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#define B_PCH_FIA_PCR_L25O (BIT7 | BIT6 | BIT5 | BIT4)
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#define B_PCH_FIA_PCR_L26O (BIT11 | BIT10 | BIT9 | BIT8)
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#define B_PCH_FIA_PCR_L27O (BIT15 | BIT14 | BIT13 | BIT12)
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#define B_PCH_FIA_PCR_L28O (BIT19 | BIT18 | BIT17 | BIT16)
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#define B_PCH_FIA_PCR_L29O (BIT23 | BIT22 | BIT21 | BIT20)
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#endif
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