/** @file
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Register names for DMI and OP-DMI
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Conventions:
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- Register definition format:
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Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
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- Prefix:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register size
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Definitions beginning with "N_" are the bit position
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- [GenerationName]:
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Three letter acronym of the generation is used .
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Register name without GenerationName applies to all generations.
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- [ComponentName]:
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This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
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Register name without ComponentName applies to all components.
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Register that is specific to -H denoted by "_PCH_H_" in component name.
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Register that is specific to -LP denoted by "_PCH_LP_" in component name.
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- SubsystemName:
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This field indicates the subsystem name of the component that the register belongs to
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(e.g. PCIE, USB, SATA, GPIO, PMC etc.).
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- RegisterSpace:
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MEM - MMIO space register of subsystem.
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IO - IO space register of subsystem.
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PCR - Private configuration register of subsystem.
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CFG - PCI configuration space register of subsystem.
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- RegisterName:
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Full register name.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_DMI15_H_
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#define _PCH_REGS_DMI15_H_
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#define R_PCH_DMI15_PCR_MPC 0x20D8 ///< Miscellaneous Port Configuration
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#define B_PCH_DMI15_PCR_MPC_SRL BIT23 ///< Secured register lock
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#define R_PCH_DMI15_PCR_V0CTL 0x2284 ///< Virtual channel 0 resource control
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#define R_PCH_DMI15_PCR_V0STS 0x228A ///< Virtual channel 0 status
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#define R_PCH_DMI15_PCR_V1CTL 0x2290 ///< Virtual channel 1 resource control
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#define R_PCH_DMI15_PCR_V1STS 0x2296 ///< Virtual channel 1 status
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#define R_PCH_DMI15_PCR_VMCTL 0x22B0 ///< ME Virtual Channel (VCm) resource control
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#define R_PCH_DMI15_PCR_UPHWAWC 0x249C ///< Upstream Port HW Autonomous Width Control
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#define B_PCH_DMI15_PCR_UPHWAWC_TS3TW (BIT15 | BIT14 | BIT13) ///< Thermal Sensor 3 Target Width
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#define N_PCH_DMI15_PCR_UPHWAWC_TS3TW 13 ///< Thermal Sensor 3 Target Width
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#define B_PCH_DMI15_PCR_UPHWAWC_TS2TW (BIT12 | BIT11 | BIT10) ///< Thermal Sensor 2 Target Width
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#define N_PCH_DMI15_PCR_UPHWAWC_TS2TW 10 ///< Thermal Sensor 2 Target Width
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#define B_PCH_DMI15_PCR_UPHWAWC_TS1TW (BIT9 | BIT8 | BIT7) ///< Thermal Sensor 1 Target Width
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#define N_PCH_DMI15_PCR_UPHWAWC_TS1TW 7 ///< Thermal Sensor 1 Target Width
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#define B_PCH_DMI15_PCR_UPHWAWC_TS0TW (BIT6 | BIT5 | BIT4) ///< Thermal Sensor 0 Target Width
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#define N_PCH_DMI15_PCR_UPHWAWC_TS0TW 4 ///< Thermal Sensor 0 Target Width
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#define B_PCH_DMI15_PCR_UPHWAWC_TSAWEN BIT0 ///< Thermal Sensor Autonomous Width Enable
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#endif
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