/** @file
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Header file for GpioPrivateLib.
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All function in this library is available for PEI, DXE, and SMM,
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _GPIO_PRIVATE_LIB_H_
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#define _GPIO_PRIVATE_LIB_H_
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#include <GpioConfig.h>
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#include <Library/PchPcrLib.h>
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//
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// Structure for native pin data
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//
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typedef struct {
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GPIO_PAD Pad;
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GPIO_PAD_MODE Mode;
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} GPIO_PAD_NATIVE_FUNCTION;
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//
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// Below defines are based on GPIO_CONFIG structure fields
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//
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#define B_GPIO_PAD_MODE_MASK 0xF
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#define N_GPIO_PAD_MODE_BIT_POS 0
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#define B_GPIO_HOSTSW_OWN_MASK 0x3
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#define N_GPIO_HOSTSW_OWN_BIT_POS 0
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#define B_GPIO_DIRECTION_MASK 0x1F
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#define B_GPIO_DIRECTION_DIR_MASK 0x7
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#define N_GPIO_DIRECTION_DIR_BIT_POS 0
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#define B_GPIO_DIRECTION_INV_MASK 0x18
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#define N_GPIO_DIRECTION_INV_BIT_POS 3
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#define B_GPIO_OUTPUT_MASK 0x3
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#define N_GPIO_OUTPUT_BIT_POS 0
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#define N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS 0
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#define N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS 5
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#define B_GPIO_RESET_CONFIG_RESET_MASK 0x3F
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#define N_GPIO_RESET_CONFIG_OLD_RESET_TYPE BIT1
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#define B_GPIO_RESET_CONFIG_OLD_RESET_MASK 0xF
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#define N_GPIO_RESET_CONFIG_RESET_BIT_POS 0
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#define B_GPIO_RESET_CONFIG_GPD_RESET_MASK (BIT5 | BIT4)
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#define B_GPIO_RESET_CONFIG_GPP_RESET_MASK (BIT3 | BIT2)
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#define N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS 0
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#define N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS 0
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//
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// Structure for storing information about registers offset, community,
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// maximal pad number for available groups
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//
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typedef struct {
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PCH_SBI_PID Community;
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UINT16 PadOwnOffset;
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UINT16 HostOwnOffset;
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UINT16 GpiIsOffset;
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UINT16 GpiIeOffset;
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UINT16 GpiGpeStsOffset;
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UINT16 GpiGpeEnOffset;
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UINT16 SmiStsOffset;
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UINT16 SmiEnOffset;
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UINT16 NmiStsOffset;
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UINT16 NmiEnOffset;
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UINT16 PadCfgLockOffset;
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UINT16 PadCfgLockTxOffset;
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UINT16 PadCfgOffset;
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UINT16 PadPerGroup;
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} GPIO_GROUP_INFO;
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//
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// If in GPIO_GROUP_INFO structure certain register doesn't exist
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// it will have value equal to NO_REGISTER_FOR_PROPERTY
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//
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#define NO_REGISTER_FOR_PROPERTY 0xFFFF
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/**
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This procedure will retrieve address and length of GPIO info table
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@param[out] GpioGroupInfoTableLength Length of GPIO group table
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@retval Pointer to GPIO group table
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**/
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CONST GPIO_GROUP_INFO*
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GpioGetGroupInfoTable (
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OUT UINT32 *GpioGroupInfoTableLength
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);
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typedef struct {
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CONST CHAR8* GpioGroupPrefix;
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CONST GPIO_PAD FirstUniqueGpio;
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CONST CHAR8** GroupUniqueNames;
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CONST UINT32 UniqueNamesTableSize;
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} GPIO_GROUP_NAME_INFO;
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//
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// Helper macros for initializing GPIO_GROUP_NAME_INFO structures
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//
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#define GPIO_GROUP_NAME(GroupName,FirstUniqueGpio,GroupUniqueNamesTable) \
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{GroupName, FirstUniqueGpio, GroupUniqueNamesTable, ARRAY_SIZE (GroupUniqueNamesTable)}
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#define GPIO_GROUP_NAME_BASIC(GroupName) \
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{GroupName, 0, NULL, 0}
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/**
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Returns GPIO_GROUP_NAME_INFO corresponding to the give GpioPad
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@param[in] GroupIndex Group index
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@retval GPIO_GROUP_NAME_INFO* Pointer to the GPIO_GROUP_NAME_INFO
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@retval NULL If no group descriptor was found
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**/
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CONST
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GPIO_GROUP_NAME_INFO*
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GpioGetGroupNameInfo (
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IN UINT32 GroupIndex
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);
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/**
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Get GPIO Chipset ID specific to PCH generation and series
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**/
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UINT32
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GpioGetThisChipsetId (
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VOID
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);
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/**
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This procedure is used to check if GpioPad is valid for certain chipset
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@param[in] GpioPad GPIO pad
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@retval TRUE This pin is valid on this chipset
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FALSE Incorrect pin
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**/
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BOOLEAN
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GpioIsCorrectPadForThisChipset (
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IN GPIO_PAD GpioPad
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);
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/**
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Generates GPIO name from GpioPad
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This function returns pointer to the static buffer.
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@param[in] GpioPad GpioPad
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@retval CHAR8* Pointer to the GPIO name
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**/
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CHAR8*
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GpioName (
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IN GPIO_PAD GpioPad
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);
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/**
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This procedure will get value of selected gpio register
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@param[in] Group GPIO group number
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@param[in] Offset GPIO register offset
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@param[out] RegVal Value of gpio register
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_INVALID_PARAMETER Invalid group or pad number
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**/
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EFI_STATUS
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GpioGetReg (
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IN GPIO_GROUP Group,
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IN UINT32 Offset,
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OUT UINT32 *RegVal
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);
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/**
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This procedure will set value of selected gpio register
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@param[in] Group GPIO group number
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@param[in] Offset GPIO register offset
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@param[in] RegVal Value of gpio register
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_INVALID_PARAMETER Invalid group or pad number
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**/
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EFI_STATUS
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GpioSetReg (
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IN GPIO_GROUP Group,
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IN UINT32 Offset,
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IN UINT32 RegVal
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);
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/**
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This procedure is used by PchSmiDispatcher and will return information
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needed to register GPI SMI.
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@param[in] Index GPI SMI number
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@param[out] GpioPin GPIO pin
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@param[out] GpiSmiBitOffset GPI SMI bit position within GpiSmi Registers
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@param[out] GpiHostSwOwnRegAddress Address of HOSTSW_OWN register
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@param[out] GpiSmiStsRegAddress Address of GPI SMI status register
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_INVALID_PARAMETER Invalid group or pad number
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**/
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EFI_STATUS
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GpioGetPadAndSmiRegs (
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IN UINT32 Index,
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OUT GPIO_PAD *GpioPin,
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OUT UINT8 *GpiSmiBitOffset,
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OUT UINT32 *GpiHostSwOwnRegAddress,
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OUT UINT32 *GpiSmiStsRegAddress
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);
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/**
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This procedure will set GPIO Driver IRQ number
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@param[in] Irq Irq number
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_INVALID_PARAMETER Invalid IRQ number
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**/
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EFI_STATUS
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GpioSetIrq (
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IN UINT8 Irq
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);
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/**
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This function provides GPIO Community PortIDs
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@param[out] NativePinsTable Table with GPIO COMMx SBI PortIDs
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@retval Number of communities
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**/
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UINT32
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GpioGetComSbiPortIds (
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OUT PCH_SBI_PID **GpioComSbiIds
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);
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/**
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This procedure will perform special handling of GPP_A_12.
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@param[in] None
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@retval None
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**/
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VOID
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GpioA12SpecialHandling (
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VOID
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);
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//
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// Structure which stores information needed to map GPIO Group
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// to 1-Tier GPE. Configuration is needed both in PMC and GPIO IP.
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// Because GPE_DWx can handle only 32 pins only single double word can
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// be mapped at a time. Each DW for a group has different configuration in PMC and GPIO
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//
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typedef struct {
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GPIO_GROUP Group;
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UINT8 GroupDw;
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UINT8 PmcGpeDwxVal;
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UINT8 GpioGpeDwxVal;
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} GPIO_GROUP_TO_GPE_MAPPING;
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/**
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Get information for GPIO Group required to program GPIO and PMC for desired 1-Tier GPE mapping
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@param[out] GpioGroupToGpeMapping Table with GPIO Group to GPE mapping
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@param[out] GpioGroupToGpeMappingLength GPIO Group to GPE mapping table length
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**/
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VOID
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GpioGetGroupToGpeMapping (
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OUT GPIO_GROUP_TO_GPE_MAPPING **GpioGroupToGpeMapping,
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OUT UINT32 *GpioGroupToGpeMappingLength
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);
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/**
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This procedure will return Port ID of GPIO Community from GpioPad
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@param[in] GpioPad GpioPad
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@retval GpioCommunityPortId Port ID of GPIO Community
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**/
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UINT8
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GpioGetGpioCommunityPortIdFromGpioPad (
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IN GPIO_PAD GpioPad
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);
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/**
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This procedure will return PadCfg address from GpioPad
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@param[in] GpioPad GpioPad
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@retval GpioPadCfgAddress PadCfg Address of GpioPad
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**/
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UINT32
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GpioGetGpioPadCfgAddressFromGpioPad (
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IN GPIO_PAD GpioPad
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);
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/**
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This procedure is used to unlock all GPIO pads.
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This function can only be called when platform is still in HOSTIA_BOOT_SAI.
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**/
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VOID
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GpioUnlockAllPads (
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VOID
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);
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/**
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This procedure will check if GpioPad is owned by host.
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@param[in] GpioPad GPIO pad
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@retval TRUE GPIO pad is owned by host
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@retval FALSE GPIO pad is not owned by host and should not be used with GPIO lib API
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**/
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BOOLEAN
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GpioIsPadHostOwned (
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IN GPIO_PAD GpioPad
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);
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/**
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This procedure will check if GpioPad argument is valid.
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Function will check below conditions:
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- GpioPad represents a pad for current PCH
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- GpioPad belongs to valid GpioGroup
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- GPIO PadNumber is not greater than number of pads for this group
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@param[in] GpioPad GPIO pad
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@retval TRUE GPIO pad is valid and can be used with GPIO lib API
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@retval FALSE GPIO pad is invalid and cannot be used with GPIO lib API
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**/
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BOOLEAN
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GpioIsPadValid (
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IN GPIO_PAD GpioPad
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);
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/**
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This procedure will read GPIO Pad Configuration register
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@param[in] GpioPad GPIO pad
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@param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1
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@retval PadCfgRegValue PADCFG_DWx value
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**/
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UINT32
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GpioReadPadCfgReg (
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IN GPIO_PAD GpioPad,
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IN UINT8 DwReg
|
);
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/**
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This procedure will write or read GPIO Pad Configuration register
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@param[in] GpioPad GPIO pad
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@param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1
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@param[in] PadCfgAndMask Mask to be AND'ed with PADCFG reg value
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@param[in] PadCfgOrMask Mask to be OR'ed with PADCFG reg value
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@retval none
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**/
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VOID
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GpioWritePadCfgReg (
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IN GPIO_PAD GpioPad,
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IN UINT8 DwReg,
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IN UINT32 PadCfgAndMask,
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IN UINT32 PadCfgOrMask
|
);
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/**
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This procedure will set GPIO mode
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@param[in] GpioPad GPIO pad
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@param[out] PadModeValue GPIO pad mode value
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_INVALID_PARAMETER Invalid group or pad number
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**/
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EFI_STATUS
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GpioSetPadMode (
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IN GPIO_PAD GpioPad,
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IN GPIO_PAD_MODE PadModeValue
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);
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/**
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This procedure will get GPIO mode
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@param[in] GpioPad GPIO pad
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@param[out] PadModeValue GPIO pad mode value
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_INVALID_PARAMETER Invalid group or pad number
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**/
|
EFI_STATUS
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GpioGetPadMode (
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IN GPIO_PAD GpioPad,
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OUT GPIO_PAD_MODE *PadModeValue
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);
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/**
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This procedure will check if group is within DeepSleepWell.
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@param[in] Group GPIO Group
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@retval GroupWell TRUE: This is DSW Group
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FALSE: This is not DSW Group
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**/
|
BOOLEAN
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GpioIsDswGroup (
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IN GPIO_GROUP Group
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);
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/**
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The function performs GPIO Power Management programming.
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**/
|
VOID
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GpioConfigurePm (
|
VOID
|
);
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/**
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This function sets SerialIo I2C controller pins into native mode
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@param[in] SerialIoI2cControllerNumber I2C controller
|
@param[in] GpioTermination GPIO termination type
|
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@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableSerialIoI2c (
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IN UINT32 SerialIoI2cControllerNumber,
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IN GPIO_ELECTRICAL_CONFIG GpioTermination
|
);
|
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/**
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This function sets SerialIo UART controller pins into native mode
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@param[in] SerialIoUartControllerNumber UART controller
|
@param[in] HardwareFlowControl Hardware Flow control
|
@param[in] PinMuxing UART controller pin muxing
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableSerialIoUart (
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IN UINT32 SerialIoUartControllerNumber,
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IN BOOLEAN HardwareFlowControl,
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IN UINT32 PinMuxing
|
);
|
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/**
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This function sets SerialIo SPI controller pins into native mode
|
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@param[in] SerialIoSpiControllerNumber SPI controller
|
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@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableSerialIoSpi (
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IN UINT32 SerialIoSpiControllerNumber
|
);
|
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/**
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This function sets ISH I2C controller pins into native mode
|
|
@param[in] IshI2cControllerNumber I2C controller
|
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@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableIshI2c (
|
IN UINT32 IshI2cControllerNumber
|
);
|
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/**
|
This function sets ISH UART controller pins into native mode
|
|
@param[in] IshUartControllerNumber UART controller
|
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@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableIshUart (
|
IN UINT32 IshUartControllerNumber
|
);
|
|
/**
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This function sets ISH SPI controller pins into native mode
|
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@param[in] IshSpiControllerNumber SPI controller
|
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@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableIshSpi (
|
IN UINT32 IshSpiControllerNumber
|
);
|
|
/**
|
This function sets ISH GP pin into native mode
|
|
@param[in] IshGpPinNumber ISH GP pin number
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableIshGpPin (
|
IN UINT32 IshGpPinNumber
|
);
|
|
/**
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This function sets SCS SD card controller pins into native mode
|
|
@param[in] none
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableScsSdCard (
|
VOID
|
);
|
|
/**
|
This function enables SCS SD Card controller card detect pin
|
|
@param[in] none
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableScsSdCardDetect (
|
VOID
|
);
|
|
/**
|
This function sets SCS eMMC controller pins into native mode
|
|
@param[in] none
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableScsEmmc (
|
VOID
|
);
|
|
/**
|
This function sets HDA Link pins into native mode
|
|
@param[in] none
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableHdaLink (
|
VOID
|
);
|
|
/**
|
This function sets HDA DMIC pins into native mode
|
|
@param[in] DmicNumber DMIC number
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableHdaDmic (
|
IN UINT32 DmicNumber
|
);
|
|
/**
|
This function sets HDA SSP interface pins into native mode
|
|
@param[in] SspInterfaceNumber SSPx interface number
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableHdaSsp (
|
IN UINT32 SspInterfaceNumber
|
);
|
|
/**
|
This function sets HDA SSP Master Clock into native mode
|
|
@param[in] none
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableHdaSspMasterClock (
|
VOID
|
);
|
|
/**
|
This function sets HDA SoundWire interface pins into native mode
|
|
@param[in] SndwInterfaceNumber SNDWx interface number
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableHdaSndw (
|
IN UINT32 SndwInterfaceNumber
|
);
|
|
/**
|
This function sets SMBUS controller pins into native mode
|
|
@param[in] none
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableSmbus (
|
VOID
|
);
|
|
/**
|
This function sets SMBUS ALERT pins into native mode
|
|
@param[in] none
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableSmbusAlert (
|
VOID
|
);
|
|
/**
|
This function enables USB OverCurrent pins by setting
|
USB2 OCB pins into native mode
|
|
@param[in] OcPinNumber USB OC pin number
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableUsbOverCurrent (
|
IN UINTN OcPinNumber
|
);
|
|
/**
|
This function sets SATA DevSlp pins into native mode
|
|
@param[in] SataCtrlIndex SATA controller index
|
@param[in] SataPort SATA port number
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableSataDevSlpPin (
|
IN UINT32 SataCtrlIndex,
|
IN UINTN SataPort
|
);
|
|
/**
|
This function checks if SataDevSlp pin is in native mode
|
|
@param[in] SataCtrlIndex SATA controller index
|
@param[in] SataPort SATA port
|
@param[out] DevSlpPad DevSlpPad
|
This is an optional parameter and may be NULL.
|
|
@retval TRUE DevSlp is in native mode
|
FALSE DevSlp is not in native mode
|
**/
|
BOOLEAN
|
GpioIsSataDevSlpPinEnabled (
|
IN UINT32 SataCtrlIndex,
|
IN UINTN SataPort,
|
OUT GPIO_PAD *DevSlpPad OPTIONAL
|
);
|
|
/**
|
This function sets SATAGPx pin into native mode
|
|
@param[in] SataCtrlIndex SATA controller index
|
@param[in] SataPort SATA port number
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableSataGpPin (
|
IN UINT32 SataCtrlIndex,
|
IN UINTN SataPort
|
);
|
|
/**
|
This function provides SATA GP pin data
|
|
@param[in] SataCtrlIndex SATA controller index
|
@param[in] SataPort SATA port number
|
@param[out] NativePin SATA GP pin
|
**/
|
VOID
|
GpioGetSataGpPin (
|
IN UINT32 SataCtrlIndex,
|
IN UINTN SataPort,
|
OUT GPIO_PAD_NATIVE_FUNCTION *NativePin
|
);
|
|
/**
|
This function sets SATA LED pin into native mode. SATA LED indicates
|
SATA controller activity
|
|
@param[in] none
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableSataLed (
|
VOID
|
);
|
|
/**
|
Returns pad for given CLKREQ# index.
|
|
@param[in] ClkreqIndex CLKREQ# number
|
|
@return CLKREQ# pad.
|
**/
|
GPIO_PAD
|
GpioGetClkreqPad (
|
IN UINT32 ClkreqIndex
|
);
|
|
/**
|
Enables CLKREQ# pad in native mode.
|
|
@param[in] ClkreqIndex CLKREQ# number
|
|
@return none
|
**/
|
VOID
|
GpioEnableClkreq (
|
IN UINT32 ClkreqIndex
|
);
|
|
/**
|
This function sets PCHHOT pin into native mode
|
|
@param[in] none
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnablePchHot (
|
VOID
|
);
|
|
/**
|
This function sets VRALERTB pin into native mode
|
|
@param[in] none
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableVrAlert (
|
VOID
|
);
|
|
/**
|
This function sets CPU GP pins into native mode
|
|
@param[in] CpuGpPinNum CPU GP pin number
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableCpuGpPin (
|
IN UINT32 CpuGpPinNum
|
);
|
|
/**
|
This function sets CPU C10 Gate pins into native mode
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableCpuC10GatePin (
|
VOID
|
);
|
|
//
|
// DDSP_HPD pins
|
//
|
typedef enum {
|
GpioDdspHpd0 = 0x00,
|
GpioDdspHpd1 = 0x01,
|
GpioDdspHpd2 = 0x02,
|
GpioDdspHpd3 = 0x03,
|
GpioDdspHpd4 = 0x04,
|
GpioDdspHpdA = 0x10,
|
GpioDdspHpdB = 0x11,
|
GpioDdspHpdC = 0x12
|
} GPIO_DDSP_HPD;
|
|
/**
|
This function sets DDSP_HPDx pin into native mode
|
|
@param[in] DdspHpdPin DDSP_HPDx pin
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableDpHotPlugDetect (
|
IN GPIO_DDSP_HPD DdspHpdPin
|
);
|
|
/**
|
This function sets HPD, VDDEN, BKLTEN and BKLTCTL pins into native mode for eDP Panel
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableEdpPins (
|
VOID
|
);
|
|
//
|
// DDPx pins
|
//
|
typedef enum {
|
GpioDdp1 = 0x01,
|
GpioDdp2 = 0x02,
|
GpioDdp3 = 0x03,
|
GpioDdp4 = 0x04,
|
GpioDdpA = 0x10,
|
GpioDdpB = 0x11,
|
GpioDdpC = 0x12,
|
GpioDdpD = 0x13,
|
GpioDdpF = 0x15,
|
} GPIO_DDP;
|
|
/**
|
This function sets DDP pins into native mode
|
|
@param[in] DdpInterface DDPx interface
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableDpInterface (
|
IN GPIO_DDP DdpInterface
|
);
|
|
/**
|
This function configures GPIO connection between CNVi and CRF
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioConfigureCnviCrfConnection (
|
VOID
|
);
|
|
/**
|
This function enables CNVi RF Reset pin
|
**/
|
VOID
|
GpioEnableCnviRfResetPin (
|
VOID
|
);
|
|
/**
|
This function enables CNVi MODEM CLKREQ pin
|
**/
|
VOID
|
GpioEnableCnviModemClkReqPin (
|
VOID
|
);
|
|
/**
|
CNVi Bluetooth UART connection options
|
**/
|
typedef enum {
|
GpioCnviBtUartNotConnected,
|
GpioCnviBtUartToSerialIoUart0,
|
GpioCnviBtUartToIshUart0,
|
GpioCnviBtUartToExternalPads
|
} VGPIO_CNVI_BT_UART_CONNECTION_TYPE;
|
|
/**
|
This function configures virtual GPIO connection for CNVi Bluetooth UART
|
|
@param[in] ConnectionType
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioConfigureCnviBtUartConnection (
|
IN VGPIO_CNVI_BT_UART_CONNECTION_TYPE ConnectionType
|
);
|
|
/**
|
CNVi Bluetooth I2S connection options
|
**/
|
typedef enum {
|
GpioCnviBtI2sNotConnected,
|
GpioCnviBtI2sToSsp0,
|
GpioCnviBtI2sToSsp1,
|
GpioCnviBtI2sToSsp2,
|
GpioCnviBtI2sToExternalPads
|
} VGPIO_CNVI_BT_I2S_CONNECTION_TYPE;
|
|
/**
|
This function configures virtual GPIO connection for CNVi Bluetooth I2S
|
|
@param[in] ConnectionType
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioConfigureCnviBtI2sConnection (
|
IN VGPIO_CNVI_BT_I2S_CONNECTION_TYPE ConnectionType
|
);
|
|
/**
|
CNVi MultiFunction UART connection options
|
**/
|
typedef enum {
|
GpioCnviMfUart1NotConnected,
|
GpioCnviMfUart1ToSerialIoUart2,
|
GpioCnviMfUart1ToIshUart0,
|
GpioCnviMfUart1ToExternalPads
|
} VGPIO_CNVI_MF_UART1_CONNECTION_TYPE;
|
|
/**
|
This function configures virtual GPIO connection for CNVi MFUART1
|
|
@param[in] ConnectionType
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioConfigureCnviMfUart1Connection (
|
IN VGPIO_CNVI_MF_UART1_CONNECTION_TYPE ConnectionType
|
);
|
|
|
/**
|
This function sets CNVi Bluetooth Enable value
|
|
@param[in] Value CNVi BT enable value
|
0: Disable, 1: Enable
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioSetCnviBtEnState (
|
IN UINT32 Value
|
);
|
|
/**
|
CNVi Bluetooth UART connection options
|
**/
|
typedef enum {
|
GpioCnviBtIfUart = 0,
|
GpioCnviBtIfUsb,
|
} VGPIO_CNVI_BT_INTERFACE;
|
|
/**
|
This function sets CNVi Bluetooth main host interface
|
|
@param[in] BtInterface CNVi BT Interface Select value
|
GpioCnviBtIfUart: UART, GpioCnviBtIfUsb: USB
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioSetCnviBtInterface (
|
IN VGPIO_CNVI_BT_INTERFACE BtInterface
|
);
|
|
/**
|
This function sets CNVi Bluetooth Wireless Charging support
|
|
@param[in] BtWirelessCharging CNVi BT Wireless Charging support
|
0: Normal BT operation (no Wireless Charging support)
|
1: Enable BT Wireless Charging
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioSetCnviBtWirelessCharging (
|
IN UINT32 BtWirelessCharging
|
);
|
|
/**
|
This function enables and configures CNVi Bluetooth Host wake-up interrupt
|
|
@param[in] None
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioConfigureCnviBtHostWakeInt (
|
VOID
|
);
|
|
/**
|
CNVi WiFi mode
|
**/
|
typedef enum {
|
GpioCnviWiFiEnabled,
|
GpioCnviWiFiAuto
|
} VGPIO_CNVI_WIFI_MODE;
|
|
/**
|
This function sets CNVi WiFi mode
|
|
@param[in] Value CNVi WiFi Mode value
|
GpioCnviWiFiAuto: WiFi is automatically enabled/disabled by WiFi core
|
GpioCnviWiFiEnabled: WiFi is enabled regardless of WiFi core decision
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioSetCnviWifiMode (
|
IN VGPIO_CNVI_WIFI_MODE WiFiMode
|
);
|
|
/**
|
This function enables IMGU CLKOUT native pin
|
|
@param[in] None
|
|
@retval Status
|
**/
|
EFI_STATUS
|
GpioEnableImguClkOut (
|
VOID
|
);
|
|
/**
|
Power button debounce configuration
|
Debounce time can be specified in microseconds. Only certain values according
|
to below formula are supported:
|
DebounceTime = (2 ^ PADCFG_DW2.DEBOUNCE)*(glitch filter clock period).
|
RTC clock with f = 32 KHz is used for glitch filter.
|
DebounceTime = (2 ^ PADCFG_DW2.DEBOUNCE)*(31.25 us).
|
Supported DebounceTime values are following:
|
DebounceTime = 0 -> Debounce feature disabled
|
DebounceTime > 0 && < 250us -> Not supported
|
DebounceTime = 250us - 1024000us -> Supported range (DebounceTime = 250us * 2^n)
|
For values not supported by HW, they will be rounded down to closest supported one
|
|
@param[in] DebounceTime Debounce Time in microseconds
|
If Debounce Time = 0, Debouncer feature will be disabled
|
Function will set DebounceTime argument to rounded supported value
|
**/
|
VOID
|
GpioSetPwrBtnDebounceTimer (
|
IN UINT32 DebounceTime
|
);
|
|
/**
|
Configure LPC GPIO
|
**/
|
VOID
|
LpcConfigureGpio (
|
VOID
|
);
|
|
#endif // _GPIO_PRIVATE_LIB_H_
|
