/** @file
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Pcie root port policy
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_PCIE_CONFIG_H_
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#define _PCH_PCIE_CONFIG_H_
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#include <PchLimits.h>
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#define PCIE_RP_CONFIG_REVISION 3
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#define PCIE_RP_PREMEM_CONFIG_REVISION 1
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extern EFI_GUID gPcieRpConfigGuid;
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extern EFI_GUID gPcieRpPreMemConfigGuid;
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#pragma pack (push,1)
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#define PCH_PCIE_SWEQ_COEFFS_MAX 5
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typedef enum {
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PchPcieOverrideDisabled = 0,
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PchPcieL1L2Override = 0x01,
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PchPcieL1SubstatesOverride = 0x02,
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PchPcieL1L2AndL1SubstatesOverride = 0x03,
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PchPcieLtrOverride = 0x04
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} PCH_PCIE_OVERRIDE_CONFIG;
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/**
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PCIe device table entry entry
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The PCIe device table is being used to override PCIe device ASPM settings.
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To take effect table consisting of such entries must be instelled as PPI
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on gPchPcieDeviceTablePpiGuid.
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Last entry VendorId must be 0.
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**/
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typedef struct {
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UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID
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UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID
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UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings
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UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class
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UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class
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UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL)
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///< Bit 1 must be set in OverrideConfig for this field to take effect
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UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
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/**
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The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig)
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This field can be zero if only the L1 Substate value is going to be override.
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**/
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UINT16 L1SubstatesCapOffset;
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/**
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L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig)
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Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override.
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Only bit [3:0] are applicable. Other bits are ignored.
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**/
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UINT8 L1SubstatesCapMask;
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/**
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L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig)
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L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
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If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
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and only L1SubstatesCapOffset is override.
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**/
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UINT8 L1sCommonModeRestoreTime;
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/**
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L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig)
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L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
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If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
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and only L1SubstatesCapOffset is override.
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**/
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UINT8 L1sTpowerOnScale;
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/**
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L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig)
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L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
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If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
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and only L1SubstatesCapOffset is override.
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**/
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UINT8 L1sTpowerOnValue;
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/**
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SnoopLatency bit definition
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Note: All Reserved bits must be set to 0
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BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
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When clear values in bits 9:0 will be ignored
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BITS[14:13] - Reserved
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BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
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000b - 1 ns
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001b - 32 ns
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010b - 1024 ns
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011b - 32,768 ns
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100b - 1,048,576 ns
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101b - 33,554,432 ns
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110b - Reserved
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111b - Reserved
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BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
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the scale in bits 12:10
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This field takes effect only if bit 3 is set in OverrideConfig.
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**/
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UINT16 SnoopLatency;
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/**
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NonSnoopLatency bit definition
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Note: All Reserved bits must be set to 0
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BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
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When clear values in bits 9:0 will be ignored
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BITS[14:13] - Reserved
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BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
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000b - 1 ns
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001b - 32 ns
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010b - 1024 ns
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011b - 32,768 ns
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100b - 1,048,576 ns
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101b - 33,554,432 ns
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110b - Reserved
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111b - Reserved
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BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
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the scale in bits 12:10
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This field takes effect only if bit 3 is set in OverrideConfig.
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**/
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UINT16 NonSnoopLatency;
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/**
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Forces LTR override to be permanent
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The default way LTR override works is:
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rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
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This settings allows force override of LTR mechanism. If it's enabled, then:
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rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
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**/
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UINT8 ForceLtrOverride;
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UINT8 Reserved[3];
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} PCH_PCIE_DEVICE_OVERRIDE;
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enum PCH_PCIE_SPEED {
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PchPcieAuto,
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PchPcieGen1,
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PchPcieGen2,
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PchPcieGen3
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};
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///
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/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
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///
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typedef enum {
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PchPcieAspmDisabled,
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PchPcieAspmL0s,
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PchPcieAspmL1,
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PchPcieAspmL0sL1,
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PchPcieAspmAutoConfig,
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PchPcieAspmMax
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} PCH_PCIE_ASPM_CONTROL;
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/**
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Refer to PCH EDS for the PCH implementation values corresponding
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to below PCI-E spec defined ranges
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**/
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typedef enum {
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PchPcieL1SubstatesDisabled,
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PchPcieL1SubstatesL1_1,
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PchPcieL1SubstatesL1_1_2,
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PchPcieL1SubstatesMax
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} PCH_PCIE_L1SUBSTATES_CONTROL;
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enum PCH_PCIE_MAX_PAYLOAD {
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PchPcieMaxPayload128 = 0,
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PchPcieMaxPayload256,
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PchPcieMaxPayloadMax
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};
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enum PCH_PCIE_COMPLETION_TIMEOUT {
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PchPcieCompletionTO_Default,
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PchPcieCompletionTO_50_100us,
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PchPcieCompletionTO_1_10ms,
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PchPcieCompletionTO_16_55ms,
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PchPcieCompletionTO_65_210ms,
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PchPcieCompletionTO_260_900ms,
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PchPcieCompletionTO_1_3P5s,
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PchPcieCompletionTO_4_13s,
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PchPcieCompletionTO_17_64s,
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PchPcieCompletionTO_Disabled
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};
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typedef enum {
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PchPcieEqDefault = 0, ///< @deprecated since revision 3. Behaves as PchPcieEqHardware.
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PchPcieEqHardware = 1, ///< Hardware equalization
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PchPcieEqStaticCoeff = 4 ///< Fixed equalization (requires Coefficient settings per lane)
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} PCH_PCIE_EQ_METHOD;
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/**
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Represent lane specific PCIe Gen3 equalization parameters.
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**/
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typedef struct {
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UINT8 Cm; ///< Coefficient C-1
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UINT8 Cp; ///< Coefficient C+1
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UINT8 Rsvd0[2]; ///< Reserved bytes
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} PCH_PCIE_EQ_LANE_PARAM, PCH_PCIE_EQ_PARAM;
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/**
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PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.
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**/
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typedef struct {
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UINT8 Usage; ///< Purpose of given clock (see PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF
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UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 mapping with Clock numbers
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UINT8 RsvdBytes[2]; ///< Reserved byte
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} PCH_PCIE_CLOCK;
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/**
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The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.
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**/
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typedef struct {
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UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. <b>0: Disable</b>; 1: Enable.
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UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; <b>1: Enable</b>.
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UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
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UINT32 RsvdBits0 : 11; ///< Reserved bits.
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/**
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Probe CLKREQ# signal before enabling CLKREQ# based power management.
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Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts
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to verify CLKREQ# signal is connected by testing pad state before enabling CPM.
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In particular this helps to avoid issues with open-ended PCIe slots.
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This is only applicable to non hot-plug ports.
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<b>0: Disable</b>; 1: Enable.
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**/
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UINT32 ClkReqDetect : 1;
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//
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// Error handlings
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//
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UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
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/**
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Max Payload Size supported, Default <b>128B</b>, see enum PCH_PCIE_MAX_PAYLOAD
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Changes Max Payload Size Supported field in Device Capabilities of the root port.
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**/
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UINT32 MaxPayload : 2;
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UINT32 RsvdBits1 : 1; ///< Reserved fields for future expansion w/o protocol change
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UINT32 DpcEnabled : 1; ///< Downstream Port Containment. 0: Disable; <b>1: Enable</b>
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UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for Downstream Port Containment. 0: Disable; <b>1: Enable</b>
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/**
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Indicates how this root port is connected to endpoint. 0: built-in device; <b>1: slot</b>
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Built-in is incompatible with hotplug-capable ports.
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**/
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UINT32 SlotImplemented : 1;
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UINT32 RsvdBits3 : 1; ///< Placeholder for deleted field
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/**
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Determines each PCIE Port speed capability.
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<b>0: Auto</b>; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED)
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**/
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UINT8 PcieSpeed;
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/**
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PCIe Gen3 Equalization Phase 3 Method (see PCH_PCIE_EQ_METHOD).
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0: DEPRECATED, hardware equalization; <b>1: hardware equalization</b>; 4: Fixed Coefficients
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**/
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UINT8 Gen3EqPh3Method;
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UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
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UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: PCH_PCIE_COMPLETION_TIMEOUT). Default is <b>PchPcieCompletionTO_Default</b>.
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/**
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The PCH pin assigned to device PERST# signal if available, zero otherwise.
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This entry is used mainly in Gen3 software equalization flow. It is necessary for some devices
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(mainly some graphic adapters) to successfully complete the software equalization flow.
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See also DeviceResetPadActiveHigh
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**/
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UINT32 RsvdBytes0[2]; ///< Reserved bytes
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//
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// Power Management
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//
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UINT8 Aspm; ///< The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is <b>PchPcieAspmAutoConfig</b> for CNP-LP B1 it is limited to <b>PchPcieAspmL1</b>.
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UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is <b>PchPcieL1SubstatesL1_1_2</b>.
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UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
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UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
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UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Snoop Latency.
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UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Non-Snoop Latency.
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UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Mode.
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UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Multiplier.
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UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Value.
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UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
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UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
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UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Value.
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UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
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UINT32 SlotPowerLimitValue : 12; ///< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>.
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//
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// Gen3 Equalization settings
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//
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UINT32 Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>5</b>.
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UINT32 Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
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/**
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<b>(Test)</b>
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Forces LTR override to be permanent
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The default way LTR override works is:
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rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
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This settings allows force override of LTR mechanism. If it's enabled, then:
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rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
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**/
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UINT32 ForceLtrOverride : 1;
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UINT32 EnableCpm : 1; ///< Enables Clock Power Management; even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism
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UINT32 PtmEnabled : 1; ///< Enables PTM capability
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UINT32 PcieRootPortGen2PllL1CgDisable : 1; ///< Disables Gen2PLL shutdown and L1 state controller power gating
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UINT32 RsvdBits2 : 6; ///< Reserved Bits
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/**
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The number of milliseconds reference code will wait for link to exit Detect state for enabled ports
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before assuming there is no device and potentially disabling the port.
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It's assumed that the link will exit detect state before root port initialization (sufficient time
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elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful
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if device power-up seqence is controlled by BIOS or a specific device requires more time to detect.
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In case of non-common clock enabled the default timout is 15ms.
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<b>Default: 0</b>
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**/
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UINT16 DetectTimeoutMs;
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UINT16 RsvdBytes1[3]; ///< Reserved bytes
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} PCH_PCIE_ROOT_PORT_CONFIG;
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/**
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The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers
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<b>Revision 1</b>:
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- Init version
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<b>Revision 2</b>:
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- Add policy PcieRootPortGen2PllL1CgDisable in PCH_PCIE_ROOT_PORT_CONFIG.
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<b>Revision 3</b>:
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- Deleted all items related to PCIe Gen3 software equalization:
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DeviceResetPad, DeviceResetPadActiveHigh policies and two values from PCH_PCIE_EQ_METHOD enum used for Gen3EqPh3Method field
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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///
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/// These members describe the configuration of each PCH PCIe root port.
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///
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PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS];
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///
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/// Configuration of PCIe source clocks
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///
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PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS];
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///
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/// Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe lane 1, etc.
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/// Corresponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default).
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///
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PCH_PCIE_EQ_LANE_PARAM EqPh3LaneParam[PCH_MAX_PCIE_ROOT_PORTS];
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///
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/// List of coefficients used during equalization (applicable to both software and hardware EQ)
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///
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PCH_PCIE_EQ_PARAM SwEqCoeffList[PCH_PCIE_SWEQ_COEFFS_MAX];
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PCH_PCIE_EQ_PARAM Rsvd0[3];
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///
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/// <b>(Test)</b> This member describes whether PCIE root port Port 8xh Decode is enabled. <b>0: Disable</b>; 1: Enable.
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///
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UINT32 EnablePort8xhDecode : 1;
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///
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/// <b>(Test)</b> The Index of PCIe Port that is selected for Port8xh Decode (0 Based)
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///
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UINT32 PchPciePort8xhDecodePortIndex : 5;
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///
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/// This member describes whether the PCI Express Clock Gating for each root port
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/// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
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///
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UINT32 DisableRootPortClockGating : 1;
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///
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/// This member describes whether Peer Memory Writes are enabled on the platform. <b>0: Disable</b>; 1: Enable.
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///
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UINT32 EnablePeerMemoryWrite : 1;
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/**
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Compliance Test Mode shall be enabled when using Compliance Load Board.
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<b>0: Disable</b>, 1: Enable
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**/
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UINT32 ComplianceTestMode : 1;
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/**
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RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled.
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A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement,
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BIOS will always enable Function0 of a device that contains more than 0 enabled root ports.
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- <b>Enabled: One of enabled root ports get assigned to Function0.</b>
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This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location
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- Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used.
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That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17.
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NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage or disabled through policy
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In other words, it only affects ports that would become hidden because they have no device connected.
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NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY
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be used when each one of root ports 1, 9, 17:
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- is configured as PCIe and has correctly configured ClkReq signal, or
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- does not own any mPhy lanes (they are configured as SATA or USB)
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**/
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UINT32 RpFunctionSwap : 1;
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UINT32 RsvdBits0 : 22;
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/**
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PCIe device override table
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The PCIe device table is being used to override PCIe device ASPM settings.
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This is a pointer points to a 32bit address. And it's only used in PostMem phase.
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Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table.
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Last entry VendorId must be 0.
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The prototype of this policy is:
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PCH_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
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**/
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UINT32 PcieDeviceOverrideTablePtr;
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} PCH_PCIE_CONFIG;
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/**
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The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers
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<b>Revision 1</b>:
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- Init version
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- Add RpEnable in premem phase.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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Root Port enabling mask.
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Bit0 presents RP1, Bit1 presents RP2, and so on.
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0: Disable; <b>1: Enable</b>.
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**/
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UINT32 RpEnabledMask;
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UINT16 PcieImrSize; ///< PCIe IMR size in megabytes
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UINT8 PcieImrEnabled; ///< PCIe IMR. <b>0: Disable</b>; 1: Enable.
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UINT8 ImrRpSelection; ///< Index of PCIe root port that is selected for IMR (0 based)
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} PCH_PCIE_RP_PREMEM_CONFIG;
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#pragma pack (pop)
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#endif // _PCH_PCIE_CONFIG_H_
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