/** @file
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Register names for CPU registers
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<b>Conventions</b>
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- Definitions beginning with "MSR_" are MSRs
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- Definitions beginning with "R_" are registers
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- Definitions beginning with "B_" are bits within registers
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- Definitions beginning with "V_" are meaningful values of bits within the registers
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- Definitions beginning with "S_" are register sizes
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- Definitions beginning with "N_" are the bit position
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Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_REGS_H_
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#define _CPU_REGS_H_
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#define MSR_CORE_THREAD_COUNT 0x00000035
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#define B_THREAD_COUNT_MASK 0xFFFF
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#define MSR_SPCL_CHIPSET_USAGE_ADDR 0x000001FE
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///
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/// Arch-specific MSR defines in SDM
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/// @{
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#define MSR_PLATFORM_INFO 0x000000CE
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#define N_PLATFORM_INFO_MIN_RATIO 40
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#define B_PLATFORM_INFO_RATIO_MASK 0xFF
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#define N_PLATFORM_INFO_MAX_RATIO 8
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#define B_MSR_PLATFORM_INFO_BIOSGUARD_AVAIL BIT35
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#define N_MSR_PLATFORM_INFO_CONFIG_TDP_NUM_LEVELS_OFFSET 33
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#define V_CONFIG_TDP_NUM_LEVELS_MASK (BIT34 | BIT33)
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#define B_PLATFORM_INFO_TDC_TDP_LIMIT BIT29
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#define N_PLATFORM_INFO_RATIO_LIMIT 28
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#define B_PLATFORM_INFO_RATIO_LIMIT BIT28
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#define B_PLATFORM_INFO_SAMPLE_PART BIT27
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#define B_PLATFORM_INFO_SMM_SAVE_CONTROL BIT16
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#define N_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET 30
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#define B_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET BIT30
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#define B_PLATFORM_INFO_TIMED_MWAIT_SUPPORTED BIT37
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#define B_PLATFORM_INFO_EDRAM_EN BIT57
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//
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// MSR_BROADWELL_PKG_CST_CONFIG_CONTROL: related defines
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//
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#define B_TIMED_MWAIT_ENABLE BIT31 ///< @todo Remove when bitfield definition is available.
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#define V_CSTATE_LIMIT_C1 0x01
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#define V_CSTATE_LIMIT_C3 0x02
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#define V_CSTATE_LIMIT_C6 0x03
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#define V_CSTATE_LIMIT_C7 0x04
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#define V_CSTATE_LIMIT_C7S 0x05
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#define V_CSTATE_LIMIT_C8 0x06
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#define V_CSTATE_LIMIT_C9 0x07
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#define V_CSTATE_LIMIT_C10 0x08
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#define MSR_PMG_IO_CAPTURE_BASE 0x000000E4
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#define B_MSR_PMG_CST_RANGE (BIT18 | BIT17 | BIT16)
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#define V_IO_CAPT_LVL2 (0x0 << 16) ///< C3
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#define V_IO_CAPT_LVL3 (0x1 << 16) ///< C6
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#define V_IO_CAPT_LVL4 (0x2 << 16) ///< C7
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#define V_IO_CAPT_LVL5 (0x3 << 16) ///< C8
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#define V_IO_CAPT_LVL6 (0x4 << 16) ///< C9
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#define V_IO_CAPT_LVL7 (0x5 << 16) ///< C10
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#define V_IO_CAPT_LVL2_BASE_ADDR_MASK 0xFFFF
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#define MSR_TEMPERATURE_TARGET 0x000001A2
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#define B_MSR_TEMPERATURE_TARGET_TCC_OFFSET_LOCK BIT31
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#define N_MSR_TEMPERATURE_TARGET_TCC_OFFSET_LIMIT 24
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#define V_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_OFFSET_MASK 0x3F
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#define N_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_TEMPERATURE_OFFSET (16)
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#define B_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_TEMPERATURE_MASK (0xFF << 16)
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#define N_MSR_TEMPERATURE_TARGET_FAN_TEMP_TARGET_OFFSET 8
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#define B_MSR_TEMPERATURE_TARGET_FAN_TEMP_TARGET_OFFSET (0xFF << 8)
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#define B_MSR_TEMPERATURE_TARGET_TCC_OFFSET_TIME_WINDOW (0x7F)
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#define B_MSR_TEMPERATURE_TARGET_TCC_OFFSET_MASK 0xFF
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#define B_MSR_TEMPERATURE_TARGET_TCC_OFFSET_CLAMP_BIT BIT7
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#define MSR_TURBO_RATIO_LIMIT 0x000001AD
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#define N_MSR_TURBO_RATIO_LIMIT_1C 0
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#define B_MSR_TURBO_RATIO_LIMIT_1C (0xFF << 0)
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#define N_MSR_TURBO_RATIO_LIMIT_2C 8
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#define B_MSR_TURBO_RATIO_LIMIT_2C (0xFF << 8)
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#define N_MSR_TURBO_RATIO_LIMIT_3C 16
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#define B_MSR_TURBO_RATIO_LIMIT_3C (0xFF << 16)
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#define N_MSR_TURBO_RATIO_LIMIT_4C 24
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#define B_MSR_TURBO_RATIO_LIMIT_4C (0xFF << 24)
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#define N_MSR_TURBO_RATIO_LIMIT_5C 32
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#define B_MSR_TURBO_RATIO_LIMIT_5C (0xFF << 32)
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#define N_MSR_TURBO_RATIO_LIMIT_6C 40
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#define B_MSR_TURBO_RATIO_LIMIT_6C (0xFF << 40)
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#define N_MSR_TURBO_RATIO_LIMIT_7C 48
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#define B_MSR_TURBO_RATIO_LIMIT_7C (0xFF << 48)
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#define N_MSR_TURBO_RATIO_LIMIT_8C 56
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#define B_MSR_TURBO_RATIO_LIMIT_8C (0xFF << 56)
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#define MSR_IA32_FEATURE_CONFIG 0x0000013C
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#define B_IA32_FEATURE_CONFIG_AES_DIS BIT1
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#define B_IA32_FEATURE_CONFIG_LOCK BIT0
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//
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// MSRs for SMM State Save Register
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//
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#define MSR_SMM_MCA_CAP 0x0000017D
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#define B_TARGETED_SMI BIT56
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#define N_TARGETED_SMI 56
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#define B_SMM_CPU_SVRSTR BIT57
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#define N_SMM_CPU_SVRSTR 57
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#define B_SMM_CODE_ACCESS_CHK BIT58
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#define N_SMM_CODE_ACCESS_CHK 58
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#define B_LONG_FLOW_INDICATION BIT59
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#define N_LONG_FLOW_INDICATION 59
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#define MSR_SMM_FEATURE_CONTROL 0x000004E0
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#define B_SMM_FEATURE_CONTROL_LOCK BIT0
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#define B_SMM_CPU_SAVE_EN BIT1
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#define B_SMM_CODE_CHK_EN BIT2
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/// @}
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///
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/// Bit defines for MSRs defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h.
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/// @{
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//
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// Number of fixed MTRRs
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//
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#define V_FIXED_MTRR_NUMBER 11
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//
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// Number of variable MTRRs
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//
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#define V_MAXIMUM_VARIABLE_MTRR_NUMBER 10
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//
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// Bit defines for MSR_IA32_MTRR_DEF_TYPE
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//
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#define B_CACHE_MTRR_VALID BIT11
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#define B_CACHE_FIXED_MTRR_VALID BIT10
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//
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// Bit defines for MSR_IA32_DEBUG_INTERFACE
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//
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#define B_DEBUG_INTERFACE_ENABLE BIT0
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#define B_DEBUG_INTERFACE_LOCK BIT30
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#define B_DEBUG_INTERFACE_DEBUG_STATUS BIT31
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/// @}
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///
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/// Other defines
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///
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#ifndef TRIGGER_MODE_EDGE
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#define TRIGGER_MODE_EDGE 0x00
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#endif
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#ifndef TRIGGER_MODE_LEVEL
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#define TRIGGER_MODE_LEVEL 0x01
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#endif
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#ifndef CPU_FEATURE_DISABLE
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#define CPU_FEATURE_DISABLE 0
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#endif
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#ifndef CPU_FEATURE_ENABLE
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#define CPU_FEATURE_ENABLE 1
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#endif
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#define CACHE_UNCACHEABLE 0
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#define CACHE_WRITECOMBINING 1
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#define CACHE_WRITETHROUGH 4
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#define CACHE_WRITEPROTECTED 5
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#define CACHE_WRITEBACK 6
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//
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// Processor Definitions
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//
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#define CPUID_FULL_STEPPING 0x0000000F
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#define CPUID_FULL_FAMILY_MODEL 0x0FFF0FF0
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#define CPUID_FULL_FAMILY_MODEL_STEPPING 0x0FFF0FFF
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#define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX 0x000806E0
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#define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO 0x000906E0
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#define CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO 0x00060670
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#define CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT 0x000A0660
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#ifndef STALL_ONE_MICRO_SECOND
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#define STALL_ONE_MICRO_SECOND 1
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#endif
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#ifndef STALL_ONE_MILLI_SECOND
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#define STALL_ONE_MILLI_SECOND 1000
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#endif
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#define BITS(x) (1 << (x))
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/**
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Notes :
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1. Bit position always starts at 0.
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2. Following macros are applicable only for Word aligned integers.
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**/
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#define BIT(Pos, Value) (1 << (Pos) & (Value))
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#define BITRANGE(From, Width, Value) (((Value) >> (From)) & ((1 << (Width)) - 1))
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///
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/// Enums for CPU Family IDs
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///
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typedef enum {
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EnumCpuCflUltUlx = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX,
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EnumCpuCflDtHalo = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO,
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EnumCpuCnlDtHalo = CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO,
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EnumCpuCmlUlt = CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT,
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EnumCpuMax = CPUID_FULL_FAMILY_MODEL
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} CPU_FAMILY;
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///
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/// Enums for CPU Stepping IDs
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///
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typedef enum {
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///
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/// Coffeelake ULX/ULT Steppings
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///
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EnumKblH0 = 9,
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EnumCflD0 = 0xA,
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/// Whiskey Lake ULT Steppings
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EnumCflW0 = 0xB,
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EnumCflV0 = 0xC,
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EnumCflMaxUltUlxStep = EnumCflV0,
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///
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/// Coffeelake DT/Halo Steppings
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///
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EnumCflU0 = 0xA,
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EnumCflB0 = 0xB,
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EnumCflP0 = 0xC,
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EnumCflR0 = 0xD,
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EnumCflMaxDtHaloStep = EnumCflR0,
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///
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/// Max Stepping
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///
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EnumCpuSteppingMax = CPUID_FULL_STEPPING
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} CPU_STEPPING;
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///
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/// Enums for CPU SKU IDs
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///
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typedef enum {
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EnumCpuUlt = 0,
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EnumCpuTrad,
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EnumCpuUlx,
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EnumCpuHalo,
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EnumCpuUnknown
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} CPU_SKU;
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///
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/// Enums for CPU Generation
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///
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typedef enum {
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EnumCflCpu = 0,
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EnumCmlCpu,
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EnumCpuUnknownGeneration = 255
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} CPU_GENERATION;
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#endif
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