/** @file
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CPU Security PreMemory Config Block.
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
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#define _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
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#define CPU_CONFIG_LIB_PREMEM_CONFIG_REVISION 5
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extern EFI_GUID gCpuConfigLibPreMemConfigGuid;
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#pragma pack (push,1)
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/**
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CPU Config Library PreMemory Configuration Structure.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Update for JTAG Power Gate comment.
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<b>Revision 3</b>:
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- Add PeciSxReset and PeciC10Reset
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<b>Revision 4</b>:
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- Add SkipMpInit
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<b>Revision 5</b>:
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- Add DpSscMarginEnable
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT32 HyperThreading : 1; ///< Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>.
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/**
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Sets the boot frequency starting from reset vector.
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- 0: Maximum battery performance.
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- <b>1: Maximum non-turbo performance</b>.
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- 2: Turbo performance.
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@note If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
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**/
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UINT32 BootFrequency : 2;
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/**
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Number of processor cores to enable.
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- <b> 0: All cores</b>
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- 1: 1 core
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- 2: 2 cores
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- 3: 3 cores
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**/
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UINT32 ActiveCoreCount : 3;
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UINT32 JtagC10PowerGateDisable : 1; ///< False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 and deeper power states for debug purpose. <b>0: False<\b>; 1: True.
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UINT32 BistOnReset : 1; ///< <b>(Test)</b> Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
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/**
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Enable or Disable Virtual Machine Extensions (VMX) feature.
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- 0: Disable
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- <b>1: Enable</b>
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**/
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UINT32 VmxEnable : 1;
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/**
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Processor Early Power On Configuration FCLK setting.
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- <b>0: 800 MHz (ULT/ULX)</b>.
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- <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.
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- 2: 400 MHz.
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- 3: Reserved.
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**/
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UINT32 FClkFrequency : 2;
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/**
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Enables a mailbox command to resolve rare PECI related Sx issues.
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@note This should only be used on systems that observe PECI Sx issues.
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- <b>0: Disable</b>
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- 1: Enable
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**/
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UINT32 PeciSxReset : 1;
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/**
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Enables the mailbox command to resolve PECI reset issues during Pkg-C10 exit.
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If Enabled, BIOS will send the CPU message to disable peci reset on C10 exit.
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The default value is <b>0: Disable</b> for CNL, and <b>1: Enable</b> for all other CPU's
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- 0: Disable
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- 1: Enable
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**/
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UINT32 PeciC10Reset : 1;
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/**
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For Fsp only, Silicon Initialization will skip MP Initialization
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(including BSP) if enabled. For non-FSP, this should always be 0.
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- <b>0: Disable</b>
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- 1: Enable
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**/
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UINT32 SkipMpInit : 1;
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/**
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Enable DisplayPort SSC range reduction
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@note This should only be used on systems that exceeds allowed SSC modulation range as defined in VESA's spec.
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- <b>0: Disable</b>
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- 1: Enable
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**/
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UINT32 DpSscMarginEnable : 1;
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UINT32 RsvdBits : 17;
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/**
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CpuRatio - Max non-turbo ratio (Flexible Ratio Boot) is set to CpuRatio. <b>0: Disabled</b> If disabled, doesn't override max-non turbo ratio.
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**/
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UINT8 CpuRatio;
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UINT8 Reserved[3]; ///< Reserved for alignment
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} CPU_CONFIG_LIB_PREMEM_CONFIG;
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#pragma pack (pop)
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#endif // _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
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