/** @file
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*
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* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
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* Copyright (c) 2016, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef __PCIE_INIT_LIB_H__
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#define __PCIE_INIT_LIB_H__
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#include <Uefi.h>
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#include <Library/IoLib.h>
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#include <Library/PlatformPciLib.h>
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#include <Regs/HisiPcieV1RegOffset.h>
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#include "PcieKernelApi.h"
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#define PCIE_AXI_SLAVE_BASE (0xb3000000)
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#define PCIE_MAX_AXI_SIZE (0x1000000)
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#define PCIE_AXI_BASE(port) (PCIE_AXI_SLAVE_BASE + port * PCIE_MAX_AXI_SIZE)
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#define PCIE_SMMU_BASE (0xb0040000)
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#define PCIE_DMA_CHANNEL_NUM (2)
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#define PCIE_DMA_RESOURCE_MODE_SIZE (0x40000)
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#define PCIE_DMA_BURST_SIZE (0x80000000)
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#define PCIE_ADDR_BASE_OFFSET 0x46C00000
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#define PCIE_ADDR_BASE_HOST_ADDR (PCIE_ADDR_BASE_OFFSET + NP_DDR_BASE_ADDR_HOST)
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#define NP_DDR_BASE_ADDR_HOST 0x236E00000ULL
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#define PCIE_GIC_MSI_ITS_BASE (0xb7010040)
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#define PCIE_INT_BASE (13824)
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#define PCIE_INT_LIMIT (PCIE_INT_BASE + 64)
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#define PCIE_NTB_MEM_SIZE (0x1000000)
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#define PCIE_NTB_BAR01_SIZE (0x10000) // 64K
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#define PCIE_NTB_BAR23_SIZE (0x800000) // 8M
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#define PCIE_NTB_BAR45_SIZE (0x800000)
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#define PCIE_IATU_END {PCIE_IATU_OUTBOUND,0,0,0}
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#define PCIE_IATU_INBOUND_MASK (0x80000000)
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#define PCIE_IATU_INDEX_MASK (0x7f)
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#define PCIE_IATU_TYPE_MASK (0x1f)
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#define PCIE_IATU_EN (0x1 << 0)
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#define PCIE_IATU_SHIFT_MODE (0x1 << 1)
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#define PCIE_IATU_BAR_MODE (0x1 << 2)
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#define PCIE_IATU_FUNC_MODE (0x1 << 3)
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#define PCIE_IATU_AT_MODE (0x1 << 4) //AT mach mode
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#define PCIE_IATU_ATTR_MODE (0x1 << 5)
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#define PCIE_IATU_TD_MODE (0x1 << 6) //TD
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#define PCIE_IATU_TC_MODE (0x1 << 7) // TC
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#define PCIE_IATU_PREFETCH_MODE (0x1 << 8)
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#define PCIE_IATU_DMA_BY_PASS_MODE (0x1 << 9) //DMA bypass untranslate
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#define PCIE_BAR_MASK_SIZE (0x800000)
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#define PCIE_BAR_TYPE_32 (0)
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#define PCIE_BAR_TYPE_64 (2)
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#define PCIE_BAR_PREFETCH_MODE (1)
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#define PCS_SDS_CFG_REG 0x204
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#define SDS_CFG_STRIDE 0x4
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#define MUX_LOS_ALOS_REG_OFFSET 0x508
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#define MUX_CFG_STRIDE 0x4
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#define CH_RXTX_STATUS_CFG_EN BIT1
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#define CH_RXTX_STATUS_CFG BIT2
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#define RegWrite(addr,data) MmioWrite32((addr), (data))
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#define RegRead(addr,data) ((data) = MmioRead32 (addr))
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#define PCIE_ASPM_DISABLE 0x0
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#define PCIE_ASPM_ENABLE 0x1
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typedef struct tagPcieDebugInfo
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{
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UINT32 pcie_rdma_start_cnt;
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UINT32 pcie_wdma_start_cnt;
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UINT64 pcie_wdma_transfer_len;
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UINT64 pcie_rdma_transfer_len;
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UINT32 pcie_rdma_fail_cnt;
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UINT32 pcie_wdma_fail_cnt;
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}pcie_debug_info_s;
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#define bdf_2_b(bdf) ((bdf >> 8) & 0xFF)
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#define bdf_2_d(bdf) ((bdf >> 3) & 0x1F)
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#define bdf_2_f(bdf) ((bdf >> 0) & 0x7)
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#define b_d_f_2_bdf(b,d,f) (((b & 0xff) << 8 ) | ((d & 0x1f) << 3) | ((f & 0x7) << 0))
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typedef UINT32 (*pcie_dma_func_int)(UINT32 ulErrno, UINT32 ulReserved);
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typedef struct {
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UINT32 ViewPort; //iATU Viewport Register
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UINT32 RegionCtrl1; //Region Control 1 Register
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UINT32 RegionCtrl2; //Region Control 2 Register
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UINT32 BaseLow; //Lower Base Address Register
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UINT32 BaseHigh; //Upper Base Address Register
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UINT32 Limit; //Limit Address Register
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UINT32 TargetLow; //Lower Target Address Register
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UINT32 TargetHigh; //Upper Target Address Register
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} PCIE_IATU_VA;
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typedef enum {
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PCIE_IATU_OUTBOUND = 0x0,
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PCIE_IATU_INBOUND = 0x1,
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} PCIE_IATU_DIR;
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typedef struct {
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PCIE_IATU_DIR IatuType;
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UINT64 IatuBase;
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UINT64 IatuSize;
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UINT64 IatuTarget;
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} PCIE_IATU;
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typedef struct {
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UINT32 IatuType;
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UINT64 IatuBase;
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UINT32 IatuLimit;
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UINT64 IatuTarget;
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UINT32 Valid;
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} PCIE_IATU_HW;
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typedef struct {
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UINT32 PortIndex;
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PCIE_PORT_INFO PortInfo;
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PCIE_IATU_HW OutBound[PCIE_MAX_OUTBOUND];
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PCIE_IATU_HW InBound[PCIE_MAX_INBOUND];
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} PCIE_DRIVER_CFG;
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typedef enum {
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PCIE_CONFIG_REG = 0x0,
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PCIE_SYS_CONTROL = 0x1,
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} PCIE_RW_MODE;
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typedef union {
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PCIE_DRIVER_CFG PcieDevice;
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PCIE_NTB_CFG NtbDevice;
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} DRIVER_CFG_U;
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typedef struct {
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VOID *MappedOutbound[PCIE_MAX_OUTBOUND];
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UINT32 OutboundType[PCIE_MAX_OUTBOUND];
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UINT32 OutboundEn[PCIE_MAX_OUTBOUND];
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} PCIE_MAPPED_IATU_ADDR;
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typedef struct {
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BOOLEAN PortIsInitilized[PCIE_MAX_ROOTBRIDGE];
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DRIVER_CFG_U Dev[PCIE_MAX_ROOTBRIDGE];
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VOID *DmaResource[PCIE_MAX_ROOTBRIDGE];
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UINT32 DmaChannel[PCIE_MAX_ROOTBRIDGE][PCIE_DMA_CHANNEL_NUM];
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VOID *RegResource[PCIE_MAX_ROOTBRIDGE];
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VOID *CfgResource[PCIE_MAX_ROOTBRIDGE];
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} PCIE_INIT_CFG;
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typedef enum {
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PCIE_MMIO_IEP_CFG = 0x1000,
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PCIE_MMIO_IEP_CTRL = 0x0,
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PCIE_MMIO_EEP_CFG = 0x9000,
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PCIE_MMIO_EEP_CTRL = 0x8000,
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} NTB_MMIO_MODE;
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typedef struct tagPcieDmaDes
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{
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UINT32 uwChanCtrl;
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UINT32 uwLen;
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UINT32 uwLocalLow;
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UINT32 uwLocalHigh;
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UINT32 uwTagetLow;
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UINT32 uwTagetHigh;
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}pcie_dma_des_s,*pcie_dma_des_ps;
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typedef enum {
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PCIE_IATU_MEM,
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PCIE_IATU_CFG = 0x4,
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PCIE_IATU_IO
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} PCIE_IATU_OUT_TYPE;
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typedef enum {
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PCIE_PAYLOAD_128B = 0,
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PCIE_PAYLOAD_256B,
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PCIE_PAYLOAD_512B,
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PCIE_PAYLOAD_1024B,
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PCIE_PAYLOAD_2048B,
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PCIE_PAYLOAD_4096B,
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PCIE_RESERVED_PAYLOAD
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} PCIE_PAYLOAD_SIZE;
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typedef struct tagPcieDfxInfo
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{
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PCIE_EP_AER_CAP0_U aer_cap0;
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PCIE_EP_AER_CAP1_U aer_cap1;
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PCIE_EP_AER_CAP2_U aer_cap2;
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PCIE_EP_AER_CAP3_U aer_cap3;
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PCIE_EP_AER_CAP4_U aer_cap4;
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PCIE_EP_AER_CAP5_U aer_cap5;
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PCIE_EP_AER_CAP6_U aer_cap6;
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UINT32 hdr_log0;
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UINT32 hdr_log1;
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UINT32 hdr_log2;
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UINT32 hdr_log3;
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PCIE_EP_AER_CAP11_U aer_cap11;
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PCIE_EP_AER_CAP12_U aer_cap12;
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PCIE_EP_AER_CAP13_U aer_cap13;
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PCIE_EP_PORTLOGIC62_U port_logic62;
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PCIE_EP_PORTLOGIC64_U port_logic64;
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PCIE_EP_PORTLOGIC66_U port_logic66;
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PCIE_EP_PORTLOGIC67_U port_logic67;
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PCIE_EP_PORTLOGIC69_U port_logic69;
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PCIE_EP_PORTLOGIC75_U port_logic75;
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PCIE_EP_PORTLOGIC76_U port_logic76;
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PCIE_EP_PORTLOGIC77_U port_logic77;
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PCIE_EP_PORTLOGIC79_U port_logic79;
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PCIE_EP_PORTLOGIC80_U port_logic80;
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PCIE_EP_PORTLOGIC81_U port_logic81;
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PCIE_EP_PORTLOGIC87_U port_logic87;
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PCIE_CTRL_10_U pcie_ctrl10;
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UINT32 slve_rerr_addr_low;
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UINT32 slve_rerr_addr_up;
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UINT32 slve_werr_addr_low;
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UINT32 slve_werr_addr_up;
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UINT32 pcie_state4;
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UINT32 pcie_state5;
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}PCIE_DFX_INFO_S;
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VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode);
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UINT32 PcieIsLinkDown(UINT32 Port);
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BOOLEAN PcieIsLinkUp(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port);
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EFI_STATUS PcieWaitLinkUp(UINT32 Port);
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EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable);
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#endif
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