/** @file
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*
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* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
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* Copyright (c) 2016, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include "PcieInit.h"
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/PcdLib.h>
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#include <Library/OemMiscLib.h>
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#include <Library/PlatformPciLib.h>
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extern VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value);
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extern EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port);
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extern EFI_STATUS PciePortInit (UINT32 soctype, UINT32 HostBridgeNum, PCIE_DRIVER_CFG *PcieCfg);
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PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_ROOTBRIDGE] =
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{
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//Port 0
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{
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0x0, //Portindex
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{
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PCIE_ROOT_COMPLEX, //PortType
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PCIE_WITDH_X8, //PortWidth
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PCIE_GEN3_0, //PortGen
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}, //PortInfo
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},
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//Port 1
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{
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0x1, //Portindex
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{
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PCIE_ROOT_COMPLEX, //PortType
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PCIE_WITDH_X8, //PortWidth
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PCIE_GEN3_0, //PortGen
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},
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},
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//Port 2
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{
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0x2, //Portindex
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{
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PCIE_ROOT_COMPLEX, //PortType
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PCIE_WITDH_X8, //PortWidth
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PCIE_GEN3_0, //PortGen
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},
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},
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//Port 3
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{
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0x3, //Portindex
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{
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PCIE_ROOT_COMPLEX, //PortType
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PCIE_WITDH_X8, //PortWidth
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PCIE_GEN3_0, //PortGen
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},
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},
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//Port 4
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{
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0x4, //Portindex
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{
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PCIE_ROOT_COMPLEX, //PortType
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PCIE_WITDH_X8, //PortWidth
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PCIE_GEN3_0, //PortGen
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},
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},
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//Port 5
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{
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0x5, //Portindex
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{
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PCIE_ROOT_COMPLEX, //PortType
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PCIE_WITDH_X8, //PortWidth
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PCIE_GEN3_0, //PortGen
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},
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},
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//Port 6
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{
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0x6, //Portindex
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{
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PCIE_ROOT_COMPLEX, //PortType
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PCIE_WITDH_X8, //PortWidth
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PCIE_GEN3_0, //PortGen
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},
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},
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//Port 7
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{
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0x7, //Portindex
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{
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PCIE_ROOT_COMPLEX, //PortType
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PCIE_WITDH_X8, //PortWidth
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PCIE_GEN3_0, //PortGen
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},
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},
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};
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EFI_STATUS
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PcieInitEntry (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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UINT32 Port;
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EFI_STATUS Status = EFI_SUCCESS;
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UINT32 HostBridgeNum = 0;
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UINT32 soctype = 0;
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UINT32 PcieRootBridgeMask;
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if (!OemIsMpBoot())
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{
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PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask);
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}
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else
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{
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PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask2P);
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}
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soctype = PcdGet32(Pcdsoctype);
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for (HostBridgeNum = 0; HostBridgeNum < PCIE_MAX_HOSTBRIDGE; HostBridgeNum++) {
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for (Port = 0; Port < PCIE_MAX_ROOTBRIDGE; Port++) {
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/*
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Host Bridge may contain lots of root bridges.
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Each Host bridge have PCIE_MAX_ROOTBRIDGE root bridges
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PcieRootBridgeMask have PCIE_MAX_ROOTBRIDGE*HostBridgeNum bits,
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and each bit stands for this PCIe Port is enable or not
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*/
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if (!(((( PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * HostBridgeNum))) >> Port) & 0x1)) {
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continue;
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}
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Status = PciePortInit(soctype, HostBridgeNum, &gastr_pcie_driver_cfg[Port]);
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if(EFI_ERROR(Status))
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{
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DEBUG((EFI_D_ERROR, "HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port));
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}
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}
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}
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return EFI_SUCCESS;
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}
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