/** @file
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Copyright (c) 2020 Jared McNeill. All rights reserved.
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Copyright (c) 2020 Andrey Warkentin <andrey.warkentin@gmail.com>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi.h>
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#include <Library/DebugLib.h>
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#include <Library/DmaLib.h>
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#include <Library/IoLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include "BcmGenetDxe.h"
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#define GENET_PHY_RETRY 1000
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STATIC CONST
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EFI_PHYSICAL_ADDRESS mDmaAddressLimit = FixedPcdGet64 (PcdDmaDeviceLimit) -
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FixedPcdGet64 (PcdDmaDeviceOffset);
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/**
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Read a memory-mapped device CSR.
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@param Genet[in] Pointer to GENERIC_PHY_PRIVATE_DATA instance.
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@param Offset[in] Register offset.
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@retval Value
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**/
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STATIC
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UINT32
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GenetMmioRead (
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IN GENET_PRIVATE_DATA *Genet,
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IN UINT32 Offset
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)
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{
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ASSERT ((Offset & 3) == 0);
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return MmioRead32 (Genet->RegBase + Offset);
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}
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/**
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Write a memory-mapped device CSR.
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@param Genet[in] Pointer to GENERIC_PHY_PRIVATE_DATA instance.
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@param Offset[in] Register offset.
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@param Data[in] Data to write.
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@retval Value
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**/
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STATIC
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VOID
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GenetMmioWrite (
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IN GENET_PRIVATE_DATA *Genet,
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IN UINT32 Offset,
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IN UINT32 Data
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)
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{
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ASSERT ((Offset & 3) == 0);
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MemoryFence ();
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MmioWrite32 (Genet->RegBase + Offset, Data);
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}
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/**
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Perform a GENET PHY register read.
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@param Priv[in] Pointer to GENET_PRIVATE_DATA.
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@param PhyAddr[in] PHY address.
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@param Reg[in] PHY register.
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@param Data[out] Pointer to register data read.
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@retval EFI_SUCCESS Data read successfully.
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@retval EFI_DEVICE_ERROR Failed to read data.
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**/
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EFI_STATUS
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EFIAPI
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GenetPhyRead (
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IN VOID *Priv,
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IN UINT8 PhyAddr,
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IN UINT8 Reg,
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OUT UINT16 *Data
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)
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{
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GENET_PRIVATE_DATA *Genet;
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UINTN Retry;
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UINT32 Value;
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Genet = Priv;
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Value = GENET_MDIO_READ |
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GENET_MDIO_START_BUSY |
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SHIFTIN (PhyAddr, GENET_MDIO_PMD) |
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SHIFTIN (Reg, GENET_MDIO_REG);
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GenetMmioWrite (Genet, GENET_MDIO_CMD, Value);
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for (Retry = GENET_PHY_RETRY; Retry > 0; Retry--) {
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Value = GenetMmioRead (Genet, GENET_MDIO_CMD);
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if ((Value & GENET_MDIO_START_BUSY) == 0) {
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*Data = Value & 0xffff;
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break;
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}
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gBS->Stall (10);
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}
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if (Retry == 0) {
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DEBUG ((DEBUG_ERROR,
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"%a: Timeout reading PhyAddr %d, Reg %d\n", __FUNCTION__, PhyAddr, Reg));
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return EFI_DEVICE_ERROR;
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}
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return EFI_SUCCESS;
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}
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/**
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Perform a GENET PHY register write.
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@param Priv[in] Pointer to GENET_PRIVATE_DATA.
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@param PhyAddr[in] PHY address.
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@param Reg[in] PHY register.
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@param Data[in] Pointer to register data to write.
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@retval EFI_SUCCESS Data written successfully.
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@retval EFI_DEVICE_ERROR Failed to write data.
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**/
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EFI_STATUS
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EFIAPI
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GenetPhyWrite (
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IN VOID *Priv,
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IN UINT8 PhyAddr,
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IN UINT8 Reg,
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IN UINT16 Data
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)
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{
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GENET_PRIVATE_DATA *Genet;
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UINTN Retry;
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UINT32 Value;
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Genet = Priv;
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Value = GENET_MDIO_WRITE |
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GENET_MDIO_START_BUSY |
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SHIFTIN (PhyAddr, GENET_MDIO_PMD) |
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SHIFTIN (Reg, GENET_MDIO_REG);
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GenetMmioWrite (Genet, GENET_MDIO_CMD, Value | Data);
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for (Retry = GENET_PHY_RETRY; Retry > 0; Retry--) {
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Value = GenetMmioRead (Genet, GENET_MDIO_CMD);
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if ((Value & GENET_MDIO_START_BUSY) == 0) {
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break;
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}
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gBS->Stall (10);
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}
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if (Retry == 0) {
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DEBUG ((DEBUG_ERROR,
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"%a: Timeout writing PhyAddr %d, Reg %d\n", __FUNCTION__, PhyAddr, Reg));
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return EFI_DEVICE_ERROR;
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}
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return EFI_SUCCESS;
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}
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/**
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Process a PHY link speed change (e.g. with MAC layer).
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@param Priv[in] Pointer to GENET_PRIVATE_DATA.
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@param Speed[in] Speed setting.
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@param Duplex[in] Duplex setting.
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**/
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VOID
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EFIAPI
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GenetPhyConfigure (
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IN VOID *Priv,
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IN GENERIC_PHY_SPEED Speed,
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IN GENERIC_PHY_DUPLEX Duplex
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)
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{
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GENET_PRIVATE_DATA *Genet;
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UINT32 Value;
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Genet = Priv;
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Value = GenetMmioRead (Genet, GENET_EXT_RGMII_OOB_CTRL);
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Value &= ~GENET_EXT_RGMII_OOB_OOB_DISABLE;
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Value |= GENET_EXT_RGMII_OOB_RGMII_LINK;
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Value |= GENET_EXT_RGMII_OOB_RGMII_MODE_EN;
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if (Genet->PhyMode == GENET_PHY_MODE_RGMII) {
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Value |= GENET_EXT_RGMII_OOB_ID_MODE_DISABLE;
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} else {
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Value &= ~GENET_EXT_RGMII_OOB_ID_MODE_DISABLE;
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}
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GenetMmioWrite (Genet, GENET_EXT_RGMII_OOB_CTRL, Value);
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Value = GenetMmioRead (Genet, GENET_UMAC_CMD);
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Value &= ~GENET_UMAC_CMD_SPEED;
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switch (Speed) {
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case PHY_SPEED_1000:
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Value |= SHIFTIN (GENET_UMAC_CMD_SPEED_1000, GENET_UMAC_CMD_SPEED);
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break;
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case PHY_SPEED_100:
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Value |= SHIFTIN (GENET_UMAC_CMD_SPEED_100, GENET_UMAC_CMD_SPEED);
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break;
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default:
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Value |= SHIFTIN (GENET_UMAC_CMD_SPEED_10, GENET_UMAC_CMD_SPEED);
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break;
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}
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if (Duplex == PHY_DUPLEX_FULL) {
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Value &= ~GENET_UMAC_CMD_HD_EN;
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} else {
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Value |= GENET_UMAC_CMD_HD_EN;
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}
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GenetMmioWrite (Genet, GENET_UMAC_CMD, Value);
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}
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/**
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Extra action to run after a PHY reset. This adds the appropriate clock
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delay based on the PHY mode.
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@param Priv[in] Pointer to GENET_PRIVATE_DATA.
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**/
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EFI_STATUS
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EFIAPI
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GenetPhyResetAction (
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IN VOID *Priv
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)
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{
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GENET_PRIVATE_DATA *Genet;
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UINT16 Value;
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EFI_STATUS Status;
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Genet = Priv;
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Status = GenetPhyWrite (Priv, Genet->Phy.PhyAddr, BRGPHY_MII_AUXCTL,
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BRGPHY_AUXCTL_SHADOW_MISC |
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(BRGPHY_AUXCTL_SHADOW_MISC << BRGPHY_AUXCTL_MISC_READ_SHIFT));
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = GenetPhyRead (Priv, Genet->Phy.PhyAddr, BRGPHY_MII_AUXCTL, &Value);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Value &= BRGPHY_AUXCTL_MISC_DATA_MASK;
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if (Genet->PhyMode == GENET_PHY_MODE_RGMII_RXID ||
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Genet->PhyMode == GENET_PHY_MODE_RGMII_ID) {
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Value |= BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN;
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} else {
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Value &= ~BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN;
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}
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Status = GenetPhyWrite (Priv, Genet->Phy.PhyAddr, BRGPHY_MII_AUXCTL,
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BRGPHY_AUXCTL_MISC_WRITE_EN | BRGPHY_AUXCTL_SHADOW_MISC | Value);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = GenetPhyWrite (Priv, Genet->Phy.PhyAddr, BRGPHY_MII_SHADOW_1C,
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BRGPHY_SHADOW_1C_CLK_CTRL);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = GenetPhyRead (Priv, Genet->Phy.PhyAddr, BRGPHY_MII_SHADOW_1C, &Value);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Value &= BRGPHY_SHADOW_1C_DATA_MASK;
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if (Genet->PhyMode == GENET_PHY_MODE_RGMII_TXID ||
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Genet->PhyMode == GENET_PHY_MODE_RGMII_ID) {
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Value |= BRGPHY_SHADOW_1C_GTXCLK_EN;
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} else {
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Value &= ~BRGPHY_SHADOW_1C_GTXCLK_EN;
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}
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Status = GenetPhyWrite (Priv, Genet->Phy.PhyAddr, BRGPHY_MII_SHADOW_1C,
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BRGPHY_SHADOW_1C_WRITE_EN | BRGPHY_SHADOW_1C_CLK_CTRL | Value);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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return EFI_SUCCESS;
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}
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/**
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Reset GENET.
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@param Genet[in] Pointer to GENET_PRIVATE_DATA.
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**/
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VOID
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GenetReset (
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IN GENET_PRIVATE_DATA *Genet
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)
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{
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UINT32 Value;
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Value = GenetMmioRead (Genet, GENET_SYS_RBUF_FLUSH_CTRL);
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Value |= GENET_SYS_RBUF_FLUSH_RESET;
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GenetMmioWrite (Genet, GENET_SYS_RBUF_FLUSH_CTRL, Value);
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gBS->Stall (10);
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Value &= ~GENET_SYS_RBUF_FLUSH_RESET;
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GenetMmioWrite (Genet, GENET_SYS_RBUF_FLUSH_CTRL, Value);
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gBS->Stall (10);
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GenetMmioWrite (Genet, GENET_SYS_RBUF_FLUSH_CTRL, 0);
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gBS->Stall (10);
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GenetMmioWrite (Genet, GENET_UMAC_CMD, 0);
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GenetMmioWrite (Genet, GENET_UMAC_CMD,
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GENET_UMAC_CMD_LCL_LOOP_EN | GENET_UMAC_CMD_SW_RESET);
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gBS->Stall (10);
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GenetMmioWrite (Genet, GENET_UMAC_CMD, 0);
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GenetMmioWrite (Genet, GENET_UMAC_MIB_CTRL,
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GENET_UMAC_MIB_RESET_RUNT | GENET_UMAC_MIB_RESET_RX | GENET_UMAC_MIB_RESET_TX);
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GenetMmioWrite (Genet, GENET_UMAC_MIB_CTRL, 0);
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GenetMmioWrite (Genet, GENET_UMAC_MAX_FRAME_LEN, GENET_MAX_PACKET_SIZE);
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Value = GenetMmioRead (Genet, GENET_RBUF_CTRL);
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Value |= GENET_RBUF_ALIGN_2B;
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GenetMmioWrite (Genet, GENET_RBUF_CTRL, Value);
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GenetMmioWrite (Genet, GENET_RBUF_TBUF_SIZE_CTRL, 1);
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}
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/**
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Set the station address.
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@param Genet[in] Pointer to GENET_PRIVATE_DATA.
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@param MacAddr[in] MAC address to set.
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**/
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VOID
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EFIAPI
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GenetSetMacAddress (
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IN GENET_PRIVATE_DATA *Genet,
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IN EFI_MAC_ADDRESS *MacAddr
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)
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{
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UINT32 Value;
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Value = MacAddr->Addr[3] |
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MacAddr->Addr[2] << 8 |
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MacAddr->Addr[1] << 16 |
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MacAddr->Addr[0] << 24;
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GenetMmioWrite (Genet, GENET_UMAC_MAC0, Value);
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Value = MacAddr->Addr[5] |
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MacAddr->Addr[4] << 8;
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GenetMmioWrite (Genet, GENET_UMAC_MAC1, Value);
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}
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/**
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Set a PHY mode.
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@param Genet[in] Pointer to GENET_PRIVATE_DATA.
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@param PhyMode[in] Mode to set.
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**/
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VOID
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GenetSetPhyMode (
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IN GENET_PRIVATE_DATA *Genet,
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IN GENET_PHY_MODE PhyMode
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)
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{
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UINT32 Value;
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switch (PhyMode) {
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case GENET_PHY_MODE_RGMII:
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case GENET_PHY_MODE_RGMII_RXID:
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case GENET_PHY_MODE_RGMII_TXID:
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case GENET_PHY_MODE_RGMII_ID:
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Value = GENET_SYS_PORT_MODE_EXT_GPHY;
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break;
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default:
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Value = 0;
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break;
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}
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GenetMmioWrite (Genet, GENET_SYS_PORT_CTRL, Value);
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}
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/**
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Enable TX/RX.
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@param Genet[in] Pointer to GENET_PRIVATE_DATA.
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**/
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VOID
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GenetEnableTxRx (
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IN GENET_PRIVATE_DATA *Genet
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)
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{
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UINT32 Value;
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// Start TX DMA on default queue
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Value = GenetMmioRead (Genet, GENET_TX_DMA_CTRL);
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Value |= GENET_TX_DMA_CTRL_EN |
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GENET_TX_DMA_CTRL_RBUF_EN (GENET_DMA_DEFAULT_QUEUE);
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GenetMmioWrite (Genet, GENET_TX_DMA_CTRL, Value);
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// Start RX DMA on default queue
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Value = GenetMmioRead (Genet, GENET_RX_DMA_CTRL);
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Value |= GENET_RX_DMA_CTRL_EN |
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GENET_RX_DMA_CTRL_RBUF_EN (GENET_DMA_DEFAULT_QUEUE);
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GenetMmioWrite (Genet, GENET_RX_DMA_CTRL, Value);
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// Enable transmitter and receiver
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Value = GenetMmioRead (Genet, GENET_UMAC_CMD);
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Value |= GENET_UMAC_CMD_TXEN | GENET_UMAC_CMD_RXEN;
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GenetMmioWrite (Genet, GENET_UMAC_CMD, Value);
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// Enable interrupts
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GenetMmioWrite (Genet, GENET_INTRL2_CPU_CLEAR_MASK,
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GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE);
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}
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/**
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Disable TX/RX.
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@param Genet[in] Pointer to GENET_PRIVATE_DATA.
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**/
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VOID
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GenetDisableTxRx (
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IN GENET_PRIVATE_DATA *Genet
|
)
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{
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UINT32 Value;
|
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// Disable interrupts
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GenetMmioWrite (Genet, GENET_INTRL2_CPU_SET_MASK, 0xFFFFFFFF);
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GenetMmioWrite (Genet, GENET_INTRL2_CPU_CLEAR, 0xFFFFFFFF);
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// Disable receiver
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Value = GenetMmioRead (Genet, GENET_UMAC_CMD);
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Value &= ~GENET_UMAC_CMD_RXEN;
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GenetMmioWrite (Genet, GENET_UMAC_CMD, Value);
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// Stop RX DMA
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Value = GenetMmioRead (Genet, GENET_RX_DMA_CTRL);
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Value &= ~GENET_RX_DMA_CTRL_EN;
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Value &= ~GENET_RX_DMA_CTRL_RBUF_EN (GENET_DMA_DEFAULT_QUEUE);
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GenetMmioWrite (Genet, GENET_RX_DMA_CTRL, Value);
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// Stop TX DMA
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Value = GenetMmioRead (Genet, GENET_TX_DMA_CTRL);
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Value &= ~GENET_TX_DMA_CTRL_EN;
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Value &= ~GENET_TX_DMA_CTRL_RBUF_EN (GENET_DMA_DEFAULT_QUEUE);
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GenetMmioWrite (Genet, GENET_TX_DMA_CTRL, Value);
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// Flush data in the TX FIFO
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GenetMmioWrite (Genet, GENET_UMAC_TX_FLUSH, 1);
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gBS->Stall (10);
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GenetMmioWrite (Genet, GENET_UMAC_TX_FLUSH, 0);
|
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// Disable transmitter
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Value = GenetMmioRead (Genet, GENET_UMAC_CMD);
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Value &= ~GENET_UMAC_CMD_TXEN;
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GenetMmioWrite (Genet, GENET_UMAC_CMD, Value);
|
}
|
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/**
|
Change promiscuous mode state.
|
|
@param Genet[in] Pointer to GENET_PRIVATE_DATA.
|
@param Enable[in] Promiscuous mode state.
|
|
**/
|
VOID
|
GenetSetPromisc (
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IN GENET_PRIVATE_DATA *Genet,
|
IN BOOLEAN Enable
|
)
|
{
|
UINT32 Value;
|
|
Value = GenetMmioRead (Genet, GENET_UMAC_CMD);
|
if (Enable) {
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Value |= GENET_UMAC_CMD_PROMISC;
|
} else {
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Value &= ~GENET_UMAC_CMD_PROMISC;
|
}
|
GenetMmioWrite (Genet, GENET_UMAC_CMD, Value);
|
}
|
|
/**
|
Enable the MAC filter for the Ethernet broadcast address
|
|
@param Genet[in] Pointer to GENET_PRIVATE_DATA.
|
@param Enable[in] Promiscuous mode state.
|
|
**/
|
VOID
|
GenetEnableBroadcastFilter (
|
IN GENET_PRIVATE_DATA *Genet,
|
IN BOOLEAN Enable
|
)
|
{
|
CONST EFI_MAC_ADDRESS *MacAddr;
|
UINT32 Value;
|
|
if (Enable) {
|
MacAddr = &Genet->SnpMode.CurrentAddress;
|
|
GenetMmioWrite (Genet, GENET_UMAC_MDF_ADDR0 (0),
|
MacAddr->Addr[1] | MacAddr->Addr[0] << 8);
|
GenetMmioWrite (Genet, GENET_UMAC_MDF_ADDR1 (0),
|
MacAddr->Addr[5] | MacAddr->Addr[4] << 8 |
|
MacAddr->Addr[3] << 16 | MacAddr->Addr[2] << 24);
|
|
GenetMmioWrite (Genet, GENET_UMAC_MDF_ADDR0 (1), 0xffff);
|
GenetMmioWrite (Genet, GENET_UMAC_MDF_ADDR1 (1), 0xffffffff);
|
|
Value = BIT16 | BIT15; // enable filters 0 and 1
|
} else {
|
Value = 0;
|
}
|
GenetMmioWrite (Genet, GENET_UMAC_MDF_CTRL, Value);
|
}
|
|
/**
|
Configure DMA TX and RX queues, enabling them.
|
|
@param Genet[in] Pointer to GENET_PRIVATE_DATA.
|
|
**/
|
VOID
|
GenetDmaInitRings (
|
IN GENET_PRIVATE_DATA *Genet
|
)
|
{
|
UINT8 Qid;
|
|
Qid = GENET_DMA_DEFAULT_QUEUE;
|
|
Genet->TxQueued = 0;
|
Genet->TxNext = 0;
|
Genet->TxConsIndex = 0;
|
Genet->TxProdIndex = 0;
|
|
Genet->RxConsIndex = 0;
|
Genet->RxProdIndex = 0;
|
|
// Configure TX queue
|
GenetMmioWrite (Genet, GENET_TX_SCB_BURST_SIZE, 0x08);
|
GenetMmioWrite (Genet, GENET_TX_DMA_READ_PTR_LO (Qid), 0);
|
GenetMmioWrite (Genet, GENET_TX_DMA_READ_PTR_HI (Qid), 0);
|
GenetMmioWrite (Genet, GENET_TX_DMA_CONS_INDEX (Qid), 0);
|
GenetMmioWrite (Genet, GENET_TX_DMA_PROD_INDEX (Qid), 0);
|
GenetMmioWrite (Genet, GENET_TX_DMA_RING_BUF_SIZE (Qid),
|
SHIFTIN (GENET_DMA_DESC_COUNT, GENET_TX_DMA_RING_BUF_SIZE_DESC_COUNT) |
|
SHIFTIN (GENET_MAX_PACKET_SIZE, GENET_TX_DMA_RING_BUF_SIZE_BUF_LENGTH));
|
GenetMmioWrite (Genet, GENET_TX_DMA_START_ADDR_LO (Qid), 0);
|
GenetMmioWrite (Genet, GENET_TX_DMA_START_ADDR_HI (Qid), 0);
|
GenetMmioWrite (Genet, GENET_TX_DMA_END_ADDR_LO (Qid),
|
GENET_DMA_DESC_COUNT * GENET_DMA_DESC_SIZE / 4 - 1);
|
GenetMmioWrite (Genet, GENET_TX_DMA_END_ADDR_HI (Qid), 0);
|
GenetMmioWrite (Genet, GENET_TX_DMA_MBUF_DONE_THRES (Qid), 1);
|
GenetMmioWrite (Genet, GENET_TX_DMA_FLOW_PERIOD (Qid), 0);
|
GenetMmioWrite (Genet, GENET_TX_DMA_WRITE_PTR_LO (Qid), 0);
|
GenetMmioWrite (Genet, GENET_TX_DMA_WRITE_PTR_HI (Qid), 0);
|
|
// Enable TX queue
|
GenetMmioWrite (Genet, GENET_TX_DMA_RING_CFG, (1U << Qid));
|
|
// Configure RX queue
|
GenetMmioWrite (Genet, GENET_RX_SCB_BURST_SIZE, 0x08);
|
GenetMmioWrite (Genet, GENET_RX_DMA_WRITE_PTR_LO (Qid), 0);
|
GenetMmioWrite (Genet, GENET_RX_DMA_WRITE_PTR_HI (Qid), 0);
|
GenetMmioWrite (Genet, GENET_RX_DMA_PROD_INDEX (Qid), 0);
|
GenetMmioWrite (Genet, GENET_RX_DMA_CONS_INDEX (Qid), 0);
|
GenetMmioWrite (Genet, GENET_RX_DMA_RING_BUF_SIZE (Qid),
|
SHIFTIN (GENET_DMA_DESC_COUNT, GENET_RX_DMA_RING_BUF_SIZE_DESC_COUNT) |
|
SHIFTIN (GENET_MAX_PACKET_SIZE, GENET_RX_DMA_RING_BUF_SIZE_BUF_LENGTH));
|
GenetMmioWrite (Genet, GENET_RX_DMA_START_ADDR_LO (Qid), 0);
|
GenetMmioWrite (Genet, GENET_RX_DMA_START_ADDR_HI (Qid), 0);
|
GenetMmioWrite (Genet, GENET_RX_DMA_END_ADDR_LO (Qid),
|
GENET_DMA_DESC_COUNT * GENET_DMA_DESC_SIZE / 4 - 1);
|
GenetMmioWrite (Genet, GENET_RX_DMA_END_ADDR_HI (Qid), 0);
|
GenetMmioWrite (Genet, GENET_RX_DMA_XON_XOFF_THRES (Qid),
|
SHIFTIN (5, GENET_RX_DMA_XON_XOFF_THRES_LO) |
|
SHIFTIN (GENET_DMA_DESC_COUNT >> 4, GENET_RX_DMA_XON_XOFF_THRES_HI));
|
GenetMmioWrite (Genet, GENET_RX_DMA_READ_PTR_LO (Qid), 0);
|
GenetMmioWrite (Genet, GENET_RX_DMA_READ_PTR_HI (Qid), 0);
|
|
// Enable RX queue
|
GenetMmioWrite (Genet, GENET_RX_DMA_RING_CFG, (1U << Qid));
|
}
|
|
/**
|
Allocate DMA buffers for RX.
|
|
@param Genet[in] Pointer to GENET_PRIVATE_DATA.
|
|
@retval EFI_SUCCESS DMA buffers allocated.
|
@retval EFI_OUT_OF_RESOURCES DMA buffers could not be allocated.
|
**/
|
EFI_STATUS
|
GenetDmaAlloc (
|
IN GENET_PRIVATE_DATA *Genet
|
)
|
{
|
EFI_STATUS Status;
|
|
Genet->RxBuffer = mDmaAddressLimit;
|
Status = gBS->AllocatePages (AllocateMaxAddress, EfiBootServicesData,
|
EFI_SIZE_TO_PAGES (GENET_MAX_PACKET_SIZE * GENET_DMA_DESC_COUNT),
|
&Genet->RxBuffer);
|
if (EFI_ERROR (Status)) {
|
DEBUG ((DEBUG_ERROR,
|
"%a: Failed to allocate RX buffer: %r\n", __FUNCTION__, Status));
|
}
|
return Status;
|
}
|
|
/**
|
Given an RX buffer descriptor index, program the IO address of the buffer into the hardware.
|
|
@param Genet[in] Pointer to GENET_PRIVATE_DATA.
|
@param DescIndex[in] Index of RX buffer descriptor.
|
|
@retval EFI_SUCCESS DMA buffers allocated.
|
@retval Others Programmatic errors, as buffers come from DmaAllocateBuffer, and thus
|
cannot fail DmaMap (for the expected NonCoherentDmaLib).
|
**/
|
EFI_STATUS
|
GenetDmaMapRxDescriptor (
|
IN GENET_PRIVATE_DATA * Genet,
|
IN UINT8 DescIndex
|
)
|
{
|
EFI_STATUS Status;
|
UINTN DmaNumberOfBytes;
|
|
ASSERT (Genet->RxBufferMap[DescIndex].Mapping == NULL);
|
ASSERT (Genet->RxBuffer != 0);
|
|
DmaNumberOfBytes = GENET_MAX_PACKET_SIZE;
|
Status = DmaMap (MapOperationBusMasterWrite,
|
GENET_RX_BUFFER (Genet, DescIndex),
|
&DmaNumberOfBytes,
|
&Genet->RxBufferMap[DescIndex].PhysAddress,
|
&Genet->RxBufferMap[DescIndex].Mapping);
|
if (EFI_ERROR (Status)) {
|
DEBUG ((DEBUG_ERROR, "%a: Failed to map RX buffer: %r\n",
|
__FUNCTION__, Status));
|
return Status;
|
}
|
|
GenetMmioWrite (Genet, GENET_RX_DESC_ADDRESS_LO (DescIndex),
|
Genet->RxBufferMap[DescIndex].PhysAddress & 0xFFFFFFFF);
|
GenetMmioWrite (Genet, GENET_RX_DESC_ADDRESS_HI (DescIndex),
|
(Genet->RxBufferMap[DescIndex].PhysAddress >> 32) & 0xFFFFFFFF);
|
GenetMmioWrite (Genet, GENET_RX_DESC_STATUS (DescIndex), 0);
|
|
return EFI_SUCCESS;
|
}
|
|
/**
|
Given an RX buffer descriptor index, undo the DmaMap operation on the buffer.
|
|
@param Genet[in] Pointer to GENET_PRIVATE_DATA.
|
@param DescIndex[in] Index of RX buffer descriptor.
|
|
**/
|
VOID
|
GenetDmaUnmapRxDescriptor (
|
IN GENET_PRIVATE_DATA * Genet,
|
IN UINT8 DescIndex
|
)
|
{
|
if (Genet->RxBufferMap[DescIndex].Mapping != NULL) {
|
DmaUnmap (Genet->RxBufferMap[DescIndex].Mapping);
|
Genet->RxBufferMap[DescIndex].Mapping = NULL;
|
}
|
}
|
|
/**
|
Free DMA buffers for RX, undoing GenetDmaAlloc.
|
|
@param Genet[in] Pointer to GENET_PRIVATE_DATA.
|
@param DescIndex[in] Index of RX buffer descriptor.
|
|
**/
|
VOID
|
GenetDmaFree (
|
IN GENET_PRIVATE_DATA *Genet
|
)
|
{
|
UINTN Idx;
|
|
for (Idx = 0; Idx < GENET_DMA_DESC_COUNT; Idx++) {
|
GenetDmaUnmapRxDescriptor (Genet, Idx);
|
}
|
gBS->FreePages (Genet->RxBuffer,
|
EFI_SIZE_TO_PAGES (GENET_MAX_PACKET_SIZE * GENET_DMA_DESC_COUNT));
|
}
|
|
/**
|
Queue TX transmission, given a buffer to transmit and a TX descriptor index.
|
|
@param Genet[in] Pointer to GENET_PRIVATE_DATA.
|
@param DescIndex[in] TX descriptor index.
|
@param PhysAddr[in] Buffer to transmit.
|
@param NumberOfBytes[in] Buffer length.
|
|
**/
|
VOID
|
GenetDmaTriggerTx (
|
IN GENET_PRIVATE_DATA * Genet,
|
IN UINT8 DescIndex,
|
IN EFI_PHYSICAL_ADDRESS PhysAddr,
|
IN UINTN NumberOfBytes
|
)
|
{
|
UINT32 DescStatus;
|
|
DescStatus = GENET_TX_DESC_STATUS_SOP |
|
GENET_TX_DESC_STATUS_EOP |
|
GENET_TX_DESC_STATUS_CRC |
|
GENET_TX_DESC_STATUS_QTAG |
|
SHIFTIN (NumberOfBytes, GENET_TX_DESC_STATUS_BUFLEN);
|
|
GenetMmioWrite (Genet, GENET_TX_DESC_ADDRESS_LO (DescIndex),
|
PhysAddr & 0xFFFFFFFF);
|
GenetMmioWrite (Genet, GENET_TX_DESC_ADDRESS_HI (DescIndex),
|
(PhysAddr >> 32) & 0xFFFFFFFF);
|
GenetMmioWrite (Genet, GENET_TX_DESC_STATUS (DescIndex), DescStatus);
|
|
GenetMmioWrite (Genet, GENET_TX_DMA_PROD_INDEX (GENET_DMA_DEFAULT_QUEUE),
|
Genet->TxProdIndex);
|
}
|
|
/**
|
Simulate a "TX interrupt", return the next (completed) TX buffer to recycle.
|
|
@param Genet[in] Pointer to GENET_PRIVATE_DATA.
|
@param TxBuf[out] Location to store pointer to next TX buffer to recycle.
|
|
**/
|
VOID
|
GenetTxIntr (
|
IN GENET_PRIVATE_DATA *Genet,
|
OUT VOID **TxBuf
|
)
|
{
|
UINT32 Total;
|
|
Total = GenetTxPending (Genet);
|
if (Genet->TxQueued > 0 && Total > 0) {
|
DmaUnmap (Genet->TxBufferMap[Genet->TxNext]);
|
*TxBuf = Genet->TxBuffer[Genet->TxNext];
|
Genet->TxQueued--;
|
Genet->TxNext = (Genet->TxNext + 1) % GENET_DMA_DESC_COUNT;
|
Genet->TxConsIndex = (Genet->TxConsIndex + 1) & 0xFFFF;
|
} else {
|
*TxBuf = NULL;
|
}
|
}
|
|
UINT32
|
GenetRxPending (
|
IN GENET_PRIVATE_DATA *Genet
|
)
|
{
|
UINT32 ProdIndex;
|
UINT32 ConsIndex;
|
|
ConsIndex = GenetMmioRead (Genet,
|
GENET_RX_DMA_CONS_INDEX (GENET_DMA_DEFAULT_QUEUE)) & 0xFFFF;
|
ASSERT (ConsIndex == Genet->RxConsIndex);
|
|
ProdIndex = GenetMmioRead (Genet,
|
GENET_RX_DMA_PROD_INDEX (GENET_DMA_DEFAULT_QUEUE)) & 0xFFFF;
|
return (ProdIndex - Genet->RxConsIndex) & 0xFFFF;
|
}
|
|
UINT32
|
GenetTxPending (
|
IN GENET_PRIVATE_DATA *Genet
|
)
|
{
|
UINT32 ConsIndex;
|
|
ConsIndex = GenetMmioRead (Genet,
|
GENET_TX_DMA_CONS_INDEX (GENET_DMA_DEFAULT_QUEUE)) & 0xFFFF;
|
|
return (ConsIndex - Genet->TxConsIndex) & 0xFFFF;
|
}
|
|
VOID
|
GenetRxComplete (
|
IN GENET_PRIVATE_DATA *Genet
|
)
|
{
|
Genet->RxConsIndex = (Genet->RxConsIndex + 1) & 0xFFFF;
|
GenetMmioWrite (Genet, GENET_RX_DMA_CONS_INDEX (GENET_DMA_DEFAULT_QUEUE),
|
Genet->RxConsIndex);
|
}
|
|
/**
|
Simulate an "RX interrupt", returning the index of a completed RX buffer and
|
corresponding frame length.
|
|
@param Genet[in] Pointer to GENET_PRIVATE_DATA.
|
@param DescIndex[out] Location to store completed RX buffer index.
|
@param FrameLength[out] Location to store frame length.
|
|
@retval EFI_SUCCESS Data received.
|
@retval EFI_NOT_READY No RX buffers ready as no data received.
|
|
**/
|
EFI_STATUS
|
GenetRxIntr (
|
IN GENET_PRIVATE_DATA *Genet,
|
OUT UINT8 *DescIndex,
|
OUT UINTN *FrameLength
|
)
|
{
|
EFI_STATUS Status;
|
UINT32 Total;
|
UINT32 DescStatus;
|
|
Total = GenetRxPending (Genet);
|
if (Total > 0) {
|
*DescIndex = Genet->RxConsIndex % GENET_DMA_DESC_COUNT;
|
DescStatus = GenetMmioRead (Genet, GENET_RX_DESC_STATUS (*DescIndex));
|
*FrameLength = SHIFTOUT (DescStatus, GENET_RX_DESC_STATUS_BUFLEN);
|
Status = EFI_SUCCESS;
|
} else {
|
Status = EFI_NOT_READY;
|
}
|
|
return Status;
|
}
|
