init

hc

2024-03-22 a0752693d998599af469473b8dc239ef973a012f

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
/** @file 
 
  ACPI Memory mapped configuration space base address Description Table (MCFG). 
  Implementation based on PCI Firmware Specification Revision 3.0 final draft, 
  downloadable at http://www.pcisig.com/home 
 
  Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. 
 
  SPDX-License-Identifier: BSD-2-Clause-Patent 
 
**/ 
 
#include "AcpiPlatform.h" 
 
// 
// CSRT for ARM_CCN504 (L3 CACHE) 
// 
#define AMD_ACPI_ARM_CCN504_CSRT_REVISION 0 
#define AMD_ACPI_ARM_CCN504_VENDOR_ID     SIGNATURE_32('A','R','M','H') 
#define AMD_ACPI_ARM_CCN504_DEVICE_ID     0x510 
#define AMD_ACPI_ARM_CCN504_RESOURCE_TYPE 0x04 
#define AMD_ACPI_ARM_CCN504_DESC_VERSION  1 
#define AMD_ACPI_ARM_CCN504_HNF_COUNT     8 
#define AMD_ACPI_ARM_CCN504_BASE_ADDR     0xE8000000ULL 
#define AMD_ACPI_ARM_CCN504_CACHE_SIZE    0x00800000ULL 
 
// 
// Ensure proper (byte-packed) structure formats 
// 
#pragma pack(push, 1) 
 
typedef struct { 
  UINT32  Version; 
  UINT8   HnfRegionCount; 
  UINT8   Reserved[3]; 
  UINT64  BaseAddress; 
  UINT64  CacheSize; 
} AMD_ACPI_ARM_CCN504_CSRT_DEVICE_DESCRIPTOR; 
 
typedef struct { 
  UINT32  Length; 
  UINT16  ResourceType; 
  UINT16  ResourceSubtype; 
  UINT32  UID; 
  AMD_ACPI_ARM_CCN504_CSRT_DEVICE_DESCRIPTOR Ccn504Desc; 
} AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR; 
 
typedef struct { 
  UINT32  Length; 
  UINT32  VendorId; 
  UINT32  SubvendorId; 
  UINT16  DeviceId; 
  UINT16  SubdeviceId; 
  UINT16  Revision; 
  UINT8   Reserved[2]; 
  UINT32  SharedInfoLength; 
  AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR RsrcDesc; 
} AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP; 
 
typedef struct { 
  EFI_ACPI_DESCRIPTION_HEADER             Header; 
  AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP RsrcGroup; 
} AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE; 
 
 
STATIC AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE AcpiCsrt = { 
   AMD_ACPI_HEADER (EFI_ACPI_5_1_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE, 
                    AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE, 
                    AMD_ACPI_ARM_CCN504_CSRT_REVISION), 
  { sizeof (AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP), // UINT32  RsrcGroup.Length 
    AMD_ACPI_ARM_CCN504_VENDOR_ID,                    // UINT32  RsrcGroup.VendorId 
    0,                                                // UINT32  RsrcGroup.SubvendorId 
    AMD_ACPI_ARM_CCN504_DEVICE_ID,                    // UINT16  RsrcGroup.DeviceId 
    0,                                                // UINT16  RsrcGroup.SubdeviceId 
    0,                                                // UINT16  RsrcGroup.Revision 
    { 0 },                                            // UINT8   RsrcGroup.Reserved[] 
    0,                                                // UINT32  RsrcGroup.SharedInfoLength 
    { sizeof (AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR),  // UINT32  RsrcDesc.Length 
      AMD_ACPI_ARM_CCN504_RESOURCE_TYPE,                      // UINT16  RsrcDesc.ResourceType 
      0,                                                      // UINT16  RsrcDesc.ResourceSubtype 
      0,                                                      // UINT32  RsrcDesc.UID 
      { AMD_ACPI_ARM_CCN504_DESC_VERSION,                     // UINT32  Ccn504Desc.Version 
        AMD_ACPI_ARM_CCN504_HNF_COUNT,                        // UINT8   Ccn504Desc.HnfRegionCount 
        { 0 },                                                // UINT8   Ccn504Desc.Reserved[] 
        AMD_ACPI_ARM_CCN504_BASE_ADDR,                        // UINT64  Ccn504Desc.BaseAddress 
        AMD_ACPI_ARM_CCN504_CACHE_SIZE,                       // UINT64  Ccn504Desc.CacheSize 
      }, 
    }, 
  }, 
}; 
 
#pragma pack(pop) 
 
VOID* CONST ReferenceAcpiTable = &AcpiCsrt;