/** @file
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*
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* Copyright (c) 2021, Rockchip Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <Base.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Soc.h>
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void DebugPrintHex(void *buf, UINT32 width, UINT32 len)
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{
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UINT32 i,j;
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UINT8 *p8 = (UINT8 *) buf;
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UINT16 *p16 = (UINT16 *) buf;
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UINT32 *p32 =(UINT32 *) buf;
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j = 0;
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for (i = 0; i < len; i++) {
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if (j == 0) {
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DebugPrint(DEBUG_ERROR, "%p + 0x%x:",buf, i * width);
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}
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if (width == 4) {
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DebugPrint(DEBUG_ERROR, "0x%08x,", p32[i]);
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} else if (width == 2) {
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DebugPrint(DEBUG_ERROR, "0x%04x,", p16[i]);
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} else {
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DebugPrint(DEBUG_ERROR, "0x%02x,", p8[i]);
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}
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if (++j >= (16/width)) {
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j = 0;
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DebugPrint(DEBUG_ERROR, "\n","");
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}
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}
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DebugPrint(DEBUG_ERROR, "\n","");
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}
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void
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EFIAPI
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DwEmmcDxeIoMux(void)
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{
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/* sdmmc0 iomux */
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}
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void
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EFIAPI
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SdhciEmmcDxeIoMux(void)
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{
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/* sdmmc0 iomux */
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BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
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BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
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BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
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}
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#define NS_CRU_BASE 0xFD7C0000
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#define CRU_CLKSEL_CON59 0x03EC
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#define CRU_CLKSEL_CON78 0x0438
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void
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EFIAPI
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Rk806SpiIomux(void)
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{
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/* io mux */
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//BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
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//BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
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PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
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PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
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MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
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}
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void
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EFIAPI
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NorFspiIomux(void)
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{
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/* io mux */
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MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
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(((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
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#define FSPI_M1
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#if defined(FSPI_M0)
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/*FSPI M0*/
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BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
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BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
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BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
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#elif defined(FSPI_M1)
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/*FSPI M1*/
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BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
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BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
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BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
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#else
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/*FSPI M2*/
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BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
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BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
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BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
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#endif
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}
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UINT32
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EFIAPI
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I2cGetBase (
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UINT32 id
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)
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{
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UINT32 Base = 0;
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switch (id) {
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case 0:
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Base = 0xFD880000;
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break;
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case 1:
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Base = 0xFEA90000;
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/* io mux */
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//BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
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//PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
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break;
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case 2:
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Base = 0xFEAA0000;
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/* io mux */
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BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
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BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
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PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
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PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
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break;
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case 3:
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Base = 0xFEAB0000;
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break;
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case 4:
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Base = 0xFEAC0000;
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break;
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case 5:
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Base = 0xFEAD0000;
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break;
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default:
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break;
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}
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return Base;
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}
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#define GPIO4_BASE 0xFEC50000
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#define GPIO_SWPORT_DR_L 0x0000
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#define GPIO_SWPORT_DDR_L 0x0008
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void
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EFIAPI
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UsbPortPowerEnable (void)
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{
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MmioWrite32(GPIO4_BASE + GPIO_SWPORT_DR_L, (0x0100UL << 16) | 0x0100);
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MmioWrite32(GPIO4_BASE + GPIO_SWPORT_DDR_L, (0x0100UL << 16) | 0x0100);
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}
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void
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EFIAPI
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Usb2PhySuspend (void)
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{
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MmioWrite32(0xfd5d4008, 0x20000000);
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MmioWrite32(0xfd5d8008, 0x20000000);
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MmioWrite32(0xfd5dc008, 0x20000000);
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}
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void
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EFIAPI
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Usb2PhyResume (void)
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{
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MmioWrite32(0xfd5d4008, 0x20000000);
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MmioWrite32(0xfd5d8008, 0x20000000);
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MmioWrite32(0xfd5dc008, 0x20000000);
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MmioWrite32(0xfd7f0a10, 0x07000700);
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MmioWrite32(0xfd7f0a10, 0x07000000);
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}
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void
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EFIAPI
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Pcie30IoInit(void)
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{
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/* Set reset and power IO to gpio output mode */
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MmioWrite32(0xFD5F808C, 0xf << (8 + 16)); /* gpio4b6 to gpio mode -> reset */
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MmioWrite32(0xFEC50008, 0x40004000); /* output */
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MmioWrite32(0xFD5F8070, 0xf << (12 + 16)); /* gpio3c3 to gpio mode -> power */
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MmioWrite32(0xFEC4000c, 0x80008); /* output */
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}
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void
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EFIAPI
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Pcie30PowerEn(void)
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{
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MmioWrite32(0xFEC40004, 0x80008); /* output high to enable power */
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}
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void
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EFIAPI
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Pcie30PeReset(BOOLEAN enable)
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{
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if(enable)
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MmioWrite32(0xFEC50000, 0x40000000); /* output low */
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else
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MmioWrite32(0xFEC50000, 0x40004000); /* output high */
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}
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