/** @file
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*
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* Processor Properties Topology Table (PPTT)
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*
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* Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <IndustryStandard/Acpi.h>
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#include "AcpiTables.h"
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#define NUM_CORES 4
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#define NUM_CLUSTERS 1
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#if (RPI_MODEL == 3)
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#define CORTEX_L1D_SIZE SIZE_16KB
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#define CORTEX_L1D_SETS 64
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#define CORTEX_L1D_ASSC 4
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#define CORTEX_L1I_SIZE SIZE_16KB
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#define CORTEX_L1I_SETS 128
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#define CORTEX_L1I_ASSC 2
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#define CORTEX_L2_SIZE SIZE_512KB
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#define CORTEX_L2_SETS 512
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#define CORTEX_L2_ASSC 16
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#elif (RPI_MODEL == 4)
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#define CORTEX_L1D_SIZE SIZE_32KB
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#define CORTEX_L1D_SETS 256
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#define CORTEX_L1D_ASSC 2
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#define CORTEX_L1I_SIZE (3*SIZE_16KB)
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#define CORTEX_L1I_SETS 256
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#define CORTEX_L1I_ASSC 3
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#define CORTEX_L2_SIZE SIZE_1MB
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#define CORTEX_L2_SETS 1024
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#define CORTEX_L2_ASSC 16
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#endif
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#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name)
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#pragma pack(1)
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typedef struct {
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EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
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UINT32 Offset[2];
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EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
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EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
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} ACPI_6_3_PPTT_CORE;
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typedef struct {
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EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
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UINT32 Offset[1];
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EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
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ACPI_6_3_PPTT_CORE Cores[NUM_CORES];
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} ACPI_6_3_PPTT_CLUSTER;
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typedef struct {
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EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt;
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ACPI_6_3_PPTT_CLUSTER Packages[NUM_CLUSTERS];
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} ACPI_6_3_PPTT_STRUCTURE;
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#pragma pack()
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#define PPTT_CORE(pid, cid, id) { \
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{ \
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EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
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FIELD_OFFSET (ACPI_6_3_PPTT_CORE, DCache), \
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{}, \
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{ \
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EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* Not PhysicalPackage */ \
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EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \
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EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
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EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */ \
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EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* identical ignored */ \
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}, \
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FIELD_OFFSET (ACPI_6_3_PPTT_STRUCTURE, \
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Packages[pid]), /* Parent */ \
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256 * (cid) + (id), /* AcpiProcessorId */ \
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2, /* NumberOfPrivateResources */ \
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}, { \
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FIELD_OFFSET (ACPI_6_3_PPTT_STRUCTURE, \
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Packages[pid].Cores[id].DCache), \
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FIELD_OFFSET (ACPI_6_3_PPTT_STRUCTURE, \
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Packages[pid].Cores[id].ICache), \
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}, { \
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EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
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sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
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{}, \
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{ \
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1, /* SizePropertyValid */ \
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1, /* NumberOfSetsValid */ \
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1, /* AssociativityValid */ \
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1, /* AllocationTypeValid */ \
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1, /* CacheTypeValid */ \
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1, /* WritePolicyValid */ \
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1, /* LineSizeValid */ \
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}, \
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0, /* NextLevelOfCache */ \
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CORTEX_L1D_SIZE, /* Size */ \
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CORTEX_L1D_SETS, /* NumberOfSets */ \
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CORTEX_L1D_ASSC, /* Associativity */ \
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{ \
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EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
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EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
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EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
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}, \
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64 /* LineSize */ \
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}, { \
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EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
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sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
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{}, \
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{ \
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1, /* SizePropertyValid */ \
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1, /* NumberOfSetsValid */ \
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1, /* AssociativityValid */ \
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1, /* AllocationTypeValid */ \
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1, /* CacheTypeValid */ \
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0, /* WritePolicyValid */ \
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1, /* LineSizeValid */ \
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}, \
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0, /* NextLevelOfCache */ \
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CORTEX_L1I_SIZE, /* Size */ \
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CORTEX_L1I_SETS, /* NumberOfSets */ \
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CORTEX_L1I_ASSC, /* Associativity */ \
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{ \
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EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType */ \
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EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
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0, /* WritePolicy */ \
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}, \
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64 /* LineSize */ \
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} \
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}
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#define PPTT_CLUSTER(pid, cid) { \
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{ \
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EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
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FIELD_OFFSET (ACPI_6_3_PPTT_CLUSTER, L2Cache), \
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{}, \
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{ \
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EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */ \
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EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \
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EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
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EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* not Leaf */ \
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EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* identical cores */ \
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}, \
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0, /* Parent */ \
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0, /* AcpiProcessorId */ \
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1, /* NumberOfPrivateResources */ \
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}, { \
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FIELD_OFFSET (ACPI_6_3_PPTT_STRUCTURE, Packages[pid].L2Cache), \
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}, { \
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EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
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sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
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{}, \
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{ \
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1, /* SizePropertyValid */ \
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1, /* NumberOfSetsValid */ \
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1, /* AssociativityValid */ \
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1, /* AllocationTypeValid */ \
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1, /* CacheTypeValid */ \
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1, /* WritePolicyValid */ \
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1, /* LineSizeValid */ \
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}, \
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0, /* NextLevelOfCache */ \
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CORTEX_L2_SIZE, /* Size */ \
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CORTEX_L2_SETS, /* NumberOfSets */ \
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CORTEX_L2_ASSC, /* Associativity */ \
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{ \
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EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
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EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
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EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
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}, \
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64 /* LineSize */ \
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}, { \
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PPTT_CORE(pid, cid, 0), \
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PPTT_CORE(pid, cid, 1), \
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PPTT_CORE(pid, cid, 2), \
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PPTT_CORE(pid, cid, 3), \
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} \
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}
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ACPI_6_3_PPTT_STRUCTURE Pptt = {
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{
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ACPI_HEADER(EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
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ACPI_6_3_PPTT_STRUCTURE,
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EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION),
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}, {
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PPTT_CLUSTER (0, 0),
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}
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};
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VOID * CONST ReferenceAcpiTable = &Pptt;
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