/*
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* Copyright (c) 2020 , Hewlett Packard Enterprise Development LP. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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*/
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#include <IndustryStandard/RiscVOpensbi.h>
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#include <Base.h>
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#include <RiscVImpl.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_scratch.h>
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#include <sbi/sbi_trap.h>
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#include <SecMain.h>
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.text
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.align 3
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ASM_FUNC (_ModuleEntryPoint)
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/*
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* Jump to warm-boot if this is not the selected core booting,
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*/
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csrr a6, CSR_MHARTID
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li a5, FixedPcdGet32 (PcdBootHartId)
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bne a6, a5, _wait_for_boot_hart
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li ra, 0
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call _reset_regs
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/* Preload HART details
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* s7 -> HART Count
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* s8 -> HART Stack Size
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*/
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li s7, FixedPcdGet32 (PcdHartCount)
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li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
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/*
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* Setup scratch space for all the HARTs
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*
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* Scratch buffer is on the top of stack buffer
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* of each hart.
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*
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* tp : Base address of scratch buffer.
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* s7 : HART Count
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* s8 : HART Stack Size
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*/
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li tp, FixedPcdGet32 (PcdScratchRamBase)
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mul a5, s7, s8
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add tp, tp, a5
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/* Keep a copy of tp */
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add t3, tp, zero
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/* Counter */
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li t2, 1
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/* hartid 0 is mandated by ISA */
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li t1, 0
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_scratch_init:
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add tp, t3, zero
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mul a5, s8, t1
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sub tp, tp, a5
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li a5, SBI_SCRATCH_SIZE
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sub tp, tp, a5
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/* Initialize scratch space */
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/* Firmware range and size */
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li a4, FixedPcdGet32 (PcdFwStartAddress)
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li a5, FixedPcdGet32 (PcdFwEndAddress)
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sub a5, a5, a4
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sd a4, SBI_SCRATCH_FW_START_OFFSET(tp)
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sd a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)
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/*
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* Note: fw_next_arg1() uses a0, a1, and ra
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*/
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call fw_next_arg1
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sd a0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp) /* Save agr1 in scratch buffer*/
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/*
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Note: fw_next_addr()uses a0, a1, and ra
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*/
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call fw_next_addr
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sd a0, SBI_SCRATCH_NEXT_ADDR_OFFSET(tp) /* Save next address in scratch buffer*/
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li a4, PRV_S
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sd a4, SBI_SCRATCH_NEXT_MODE_OFFSET(tp) /* Save next mode in scratch buffer*/
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la a4, _start_warm
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sd a4, SBI_SCRATCH_WARMBOOT_ADDR_OFFSET(tp) /* Save warm boot address in scratch buffer*/
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la a4, platform
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sd a4, SBI_SCRATCH_PLATFORM_ADDR_OFFSET(tp) /* Save platfrom table in scratch buffer*/
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la a4, _hartid_to_scratch
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sd a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp) /* Save _hartid_to_scratch function in scratch buffer*/
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sd zero, SBI_SCRATCH_TMP0_OFFSET(tp)
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#ifdef FW_OPTIONS
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li a4, FW_OPTIONS
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sd a4, SBI_SCRATCH_OPTIONS_OFFSET(tp)
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#else
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sd zero, SBI_SCRATCH_OPTIONS_OFFSET(tp)
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#endif
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add t1, t1, t2
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/* Loop to next hart */
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blt t1, s7, _scratch_init
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/* Fill-out temporary memory with 55aa*/
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li a4, FixedPcdGet32 (PcdTemporaryRamBase)
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li a5, FixedPcdGet32 (PcdTemporaryRamSize)
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add a5, a4, a5
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1:
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li a3, 0x5AA55AA55AA55AA5
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sd a3, (a4)
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add a4, a4, __SIZEOF_POINTER__
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blt a4, a5, 1b
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/* Update boot hart flag */
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la a4, _boot_hart_done
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li a5, 1
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sd a5, (a4)
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/* Wait for boot hart */
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_wait_for_boot_hart:
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la a4, _boot_hart_done
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ld a5, (a4)
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/* Reduce the bus traffic so that boot hart may proceed faster */
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nop
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nop
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nop
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beqz a5, _wait_for_boot_hart
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_start_warm:
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li ra, 0
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call _reset_regs
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/* Disable and clear all interrupts */
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csrw CSR_MIE, zero
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csrw CSR_MIP, zero
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li s7, FixedPcdGet32 (PcdBootableHartNumber)
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li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
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la a4, platform
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/* s9 is hart_index2id array */
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REG_L s9, SBI_PLATFORM_HART_INDEX2ID_OFFSET(a4)
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/* s6 is this hart ID */
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csrr s6, CSR_MHARTID
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/*
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* Convert hart ID to scratch buffer
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* Because the hert ID maybe not in sequentially
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*/
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beqz s9, 3f
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li a4, 0
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1:
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#if __riscv_xlen == 64
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lwu a5, (s9)
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#else
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lw a5, (s9)
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#endif
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/* Branch if hart ID is matched */
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beq a5, s6, 2f
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add s9, s9, 4
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add a4, a4, 1
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/* Loop to next index */
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blt a4, s7, 1b
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li a4, -1
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2:
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add s6, a4, zero
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3:
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/* Jump to UninitializedHartWait for the non-bootable harts.
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Be aware that the stack and scratch is not set
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at this moment for this hart even the resource
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is preserved eariler for it.
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*/
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bltu s6, s7, 4f
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csrr a0, CSR_MHARTID
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j _uninitialized_hart_wait
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4:
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li s7, FixedPcdGet32 (PcdHartCount)
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/* Find the scratch space for this hart
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*
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* Scratch buffer is on the top of stack buffer
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* reserved for opensbi.
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*
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* tp: The base address of scratch buffer
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* s6: Index to scratch buffer fot this hart
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* s7: Total hart number
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* s8: Stack size for opebsbi.
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*/
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li tp, FixedPcdGet32 (PcdScratchRamBase)
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mul a5, s7, s8
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add tp, tp, a5
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mul a5, s8, s6
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sub tp, tp, a5
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li a5, SBI_SCRATCH_SIZE
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sub tp, tp, a5
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/* update the mscratch */
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csrw CSR_MSCRATCH, tp
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/*make room for Hart specific Firmware Context*/
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li a5, FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE
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sub tp, tp, a5
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/* Setup stack */
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add sp, tp, zero
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/* Setup stack for the Hart executing EFI to top of temporary ram*/
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csrr a6, CSR_MHARTID
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li a5, FixedPcdGet32 (PcdBootHartId)
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bne a6, a5, 1f
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li a4, FixedPcdGet32(PcdTemporaryRamBase)
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li a5, FixedPcdGet32(PcdTemporaryRamSize)
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add sp, a4, a5
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1:
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/* Setup trap handler */
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la a4, _trap_handler
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csrw CSR_MTVEC, a4
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/* Make sure that mtvec is updated */
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1:
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csrr a5, CSR_MTVEC
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bne a4, a5, 1b
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/* Call library constructors before jup to SEC core */
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call ProcessLibraryConstructorList
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/* Jump to SEC Core C
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* a0: HART ID
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* a1: Scratch pointer
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*/
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csrr a0, CSR_MHARTID
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csrr a1, CSR_MSCRATCH
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call SecCoreStartUpWithStack
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/* We do not expect to reach here hence just hang */
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j _start_hang
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.align 3
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.section .data, "aw"
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_boot_hart_done:
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RISCV_PTR 0
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.align 3
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.section .entry, "ax", %progbits
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.globl _hartid_to_scratch
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/*
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* a0 -> HART id (Obsoleted, keep this for the backward compatible)
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* a1 -> HART index (0-based) of this hart id
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*/
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_hartid_to_scratch:
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add sp, sp, -(3 * __SIZEOF_POINTER__)
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sd s0, (sp)
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sd s1, (__SIZEOF_POINTER__)(sp)
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sd s2, (__SIZEOF_POINTER__ * 2)(sp)
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/*
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* s0 -> HART Stack Size
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* s1 -> HART Stack End
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* s2 -> Temporary
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*/
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la s2, platform
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#if __riscv_xlen == 64
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lwu s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
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#else
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lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
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#endif
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li s2, FixedPcdGet32 (PcdHartCount)
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mul s2, s2, s0
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li s1, FixedPcdGet32 (PcdScratchRamBase)
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add s1, s1, s2
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mul s2, s0, a1
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sub s1, s1, s2
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li s2, SBI_SCRATCH_SIZE
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sub a0, s1, s2
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ld s0, (sp)
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ld s1, (__SIZEOF_POINTER__)(sp)
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ld s2, (__SIZEOF_POINTER__ * 2)(sp)
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add sp, sp, (3 * __SIZEOF_POINTER__)
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ret
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.align 3
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.section .entry, "ax", %progbits
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.globl _start_hang
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_start_hang:
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wfi
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j _start_hang
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/*
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* Uninitialized hart comes here and wait
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* for the further process.
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* a0: hart ID.
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*/
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_uninitialized_hart_wait:
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wfi
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j _uninitialized_hart_wait
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.align 3
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.section .entry, "ax", %progbits
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.align 3
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.globl _trap_handler
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_trap_handler:
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/* Swap TP and MSCRATCH */
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csrrw tp, CSR_MSCRATCH, tp
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/* Save T0 in scratch space */
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REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp)
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/* Check which mode we came from */
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csrr t0, CSR_MSTATUS
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srl t0, t0, MSTATUS_MPP_SHIFT
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and t0, t0, PRV_M
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xori t0, t0, PRV_M
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beq t0, zero, _trap_handler_m_mode
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/* We came from S-mode or U-mode */
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_trap_handler_s_mode:
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/* Set T0 to original SP */
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add t0, sp, zero
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/* Setup exception stack */
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add sp, tp, -(SBI_TRAP_REGS_SIZE)
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/* Jump to code common for all modes */
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j _trap_handler_all_mode
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/* We came from M-mode */
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_trap_handler_m_mode:
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/* Set T0 to original SP */
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add t0, sp, zero
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/* Re-use current SP as exception stack */
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add sp, sp, -(SBI_TRAP_REGS_SIZE)
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_trap_handler_all_mode:
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/* Save original SP (from T0) on stack */
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REG_S t0, SBI_TRAP_REGS_OFFSET(sp)(sp)
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/* Restore T0 from scratch space */
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REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp)
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/* Save T0 on stack */
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REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
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/* Swap TP and MSCRATCH */
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csrrw tp, CSR_MSCRATCH, tp
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/* Save MEPC and MSTATUS CSRs */
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csrr t0, CSR_MEPC
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REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
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csrr t0, CSR_MSTATUS
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REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
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REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
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#if __riscv_xlen == 32
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csrr t0, CSR_MISA
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srli t0, t0, ('H' - 'A')
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andi t0, t0, 0x1
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beq t0, zero, _skip_mstatush_save
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csrr t0, CSR_MSTATUSH
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REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
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_skip_mstatush_save:
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#endif
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/* Save all general registers except SP and T0 */
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REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp)
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REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
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REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
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REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
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REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
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REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
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REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
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REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
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REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
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REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
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REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
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REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
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REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
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REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
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REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
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REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
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REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
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REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
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REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
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REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
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REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
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REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
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REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
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REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
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REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
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REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
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REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
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REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
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REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
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REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
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/* Call C routine */
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add a0, sp, zero
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call sbi_trap_handler
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/* Restore all general registers except SP and T0 */
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REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
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REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
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REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
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REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
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REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
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REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
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REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
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REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
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REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
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REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
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REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
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REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
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REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
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REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
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REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
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REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
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REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
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REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
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REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
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REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
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REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
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REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
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REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
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REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
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REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
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REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
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REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
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REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
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REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
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/* Restore MEPC and MSTATUS CSRs */
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REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
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csrw CSR_MEPC, t0
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REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
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csrw CSR_MSTATUS, t0
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#if __riscv_xlen == 32
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csrr t0, CSR_MISA
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srli t0, t0, ('H' - 'A')
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andi t0, t0, 0x1
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beq t0, zero, _skip_mstatush_restore
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REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
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csrw CSR_MSTATUSH, t0
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_skip_mstatush_restore:
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#endif
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/* Restore T0 */
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REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
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/* Restore SP */
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REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(sp)
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mret
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.align 3
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.section .entry, "ax", %progbits
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.globl _reset_regs
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_reset_regs:
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/* flush the instruction cache */
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fence.i
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/* Reset all registers except ra, a0,a1 */
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li sp, 0
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li gp, 0
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li tp, 0
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li t0, 0
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li t1, 0
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li t2, 0
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li s0, 0
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li s1, 0
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li a2, 0
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li a3, 0
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li a4, 0
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li a5, 0
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li a6, 0
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li a7, 0
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li s2, 0
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li s3, 0
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li s4, 0
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li s5, 0
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li s6, 0
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li s7, 0
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li s8, 0
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li s9, 0
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li s10, 0
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li s11, 0
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li t3, 0
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li t4, 0
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li t5, 0
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li t6, 0
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csrw CSR_MSCRATCH, 0
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ret
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.align 3
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.section .entry, "ax", %progbits
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.global fw_prev_arg1
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fw_prev_arg1:
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/* We return previous arg1 in 'a0' */
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add a0, zero, zero
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ret
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.align 3
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.section .entry, "ax", %progbits
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.global fw_next_arg1
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fw_next_arg1:
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/* We return next arg1 in 'a0' */
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li a0, FixedPcdGet32(PcdRiscVPeiFvBase)
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ret
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.align 3
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.section .entry, "ax", %progbits
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.global fw_next_addr
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fw_next_addr:
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/* We return next address in 'a0' */
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la a0, _jump_addr
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ld a0, (a0)
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ret
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.align 3
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.section .entry, "ax", %progbits
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_jump_addr:
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RISCV_PTR SecCoreStartUpWithStack
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