/** @file
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Install Platform Hsio Ptss Table Data.
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@copyright
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Copyright 2018 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PeiCommonBoardInitLib.h"
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#include <Library/UbaHsioPtssTableConfigLib.h>
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#include <Library/SpsPeiLib.h>
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#include <Library/PchInfoLib.h>
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#include <Ppi/PchPolicy.h>
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#include <Library/HobLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Ppi/PchHsioPtssTable.h>
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#include "PchLbgHsioPtssTablesBx.h"
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#include "PchLbgHsioPtssTablesBx_Ext.h"
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#include "PchLbgHsioPtssTablesSx.h"
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#include "PchLbgHsioPtssTablesSx_Ext.h"
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#include <Guid/PlatformInfo.h>
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#include <Library/IoLib.h>
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#include <Library/EmulationConfigurationLib.h>
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#include <Library/PchMultiPchBase.h>
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#include <Ppi/DynamicSiLibraryPpi.h>
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VOID
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InstallPlatformHsioPtssTableCallback (
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IN PCH_SETUP *PchSetup,
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IN OUT PCH_POLICY_PPI *PchPolicy
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)
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{
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HSIO_PTSS_TABLES *PtssTables;
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UINT8 PtssTableIndex;
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UINT32 TableSize;
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UINT32 Entry;
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UINT8 LaneNum;
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UINT8 Index;
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UINT8 MaxSataPorts;
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UINT8 MaxsSataPorts;
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UINT8 MaxPciePorts;
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UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS];
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UINT8 PciePort;
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UINTN RpBase;
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UINTN RpDevice;
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UINTN RpFunction;
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UINT32 StrapFuseCfg;
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UINT8 PcieControllerCfg;
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EFI_STATUS Status;
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UINT16 BoardId;
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EFI_HOB_GUID_TYPE *GuidHob;
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EFI_PLATFORM_INFO *PlatformInfo;
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DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
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Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
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if (EFI_ERROR (Status)) {
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ASSERT_EFI_ERROR (Status);
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return;
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}
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switch (DynamicSiLibraryPpi->PchStepping ()) {
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case LbgA0:
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case LbgB0:
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case LbgB1:
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case LbgB2:
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case LbgB3:
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{
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PtssTables = PchLbgHsioPtss_Bx;
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TableSize = PchLbgHsioPtss_Bx_Size;
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}
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if (DynamicSiLibraryPpi->HybridSystemLevelEmulationEnabled ()) {
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PtssTables = PchLbgHsioPtss_Bx;
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TableSize = PchLbgHsioPtss_Bx_Size;
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}
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break;
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case LbgS0:
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case LbgS1:
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case LbgS2:
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{
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PtssTables = PchLbgHsioPtss_Sx;
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TableSize = PchLbgHsioPtss_Sx_Size;
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}
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if (DynamicSiLibraryPpi->HybridSystemLevelEmulationEnabled ()) {
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PtssTables = PchLbgHsioPtss_Sx;
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TableSize = PchLbgHsioPtss_Sx_Size;
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}
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break;
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default:
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PtssTables = NULL;
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TableSize = 0;
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DEBUG ((DEBUG_ERROR, "Cannot find PTSS table for this PCH Stepping\n"));
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ASSERT (FALSE);
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}
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GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
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ASSERT(GuidHob != NULL);
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PlatformInfo = GET_GUID_HOB_DATA(GuidHob);
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BoardId = PlatformInfo->BoardId;
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PtssTableIndex = 0;
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MaxSataPorts = DynamicSiLibraryPpi->GetPchMaxSataPortNum ();
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MaxsSataPorts = DynamicSiLibraryPpi->GetPchMaxsSataPortNum ();
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MaxPciePorts = DynamicSiLibraryPpi->GetPchMaxPciePortNum ();
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ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal));
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//Populate PCIe topology based on lane configuration
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CopyMem (
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PcieTopologyReal,
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PchSetup->PcieTopology,
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sizeof (PcieTopologyReal)
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);
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for (PciePort = 0; PciePort < MaxPciePorts; PciePort += 4) {
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Status = DynamicSiLibraryPpi->GetPchPcieRpDevFunByPchId (PCH_LEGACY_ID, PciePort, &RpDevice, &RpFunction);
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RpBase = DynamicSiLibraryPpi->MmPciBase (0, (UINT32) RpDevice, (UINT32) RpFunction);
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StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG);
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PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC);
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DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", PciePort, PcieControllerCfg));
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PcieTopologyReal[PciePort] = PchSetup->PcieTopology[PciePort];
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if (PcieControllerCfg != V_PCH_PCIE_STRPFUSECFG_RPC_1_1_1_1) {
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PcieTopologyReal[PciePort + 1] = PchSetup->PcieTopology[PciePort];
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}
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if (PcieControllerCfg == V_PCH_PCIE_STRPFUSECFG_RPC_4) {
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PcieTopologyReal[PciePort + 2] = PchSetup->PcieTopology[PciePort];
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PcieTopologyReal[PciePort + 3] = PchSetup->PcieTopology[PciePort];
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}
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if (PcieControllerCfg == V_PCH_PCIE_STRPFUSECFG_RPC_2_2) {
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PcieTopologyReal[PciePort + 2] = PchSetup->PcieTopology[PciePort + 2];
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PcieTopologyReal[PciePort + 3] = PchSetup->PcieTopology[PciePort + 2];
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}
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if (PcieControllerCfg == V_PCH_PCIE_STRPFUSECFG_RPC_2_1_1) {
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PcieTopologyReal[PciePort + 2] = PchSetup->PcieTopology[PciePort + 2];
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PcieTopologyReal[PciePort + 3] = PchSetup->PcieTopology[PciePort + 3];
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}
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}
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for (Index = 0; Index < MaxPciePorts; Index++) {
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DEBUG ((DEBUG_INFO, "PCIE PTSS Setup RP %d Topology = %d\n", Index, PchSetup->PcieTopology[Index]));
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DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", Index, PcieTopologyReal[Index]));
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}
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//Case 1: BoardId is known, Topology is known/unknown
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//Case 1a: SATA
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for (Index = 0; Index < MaxSataPorts; Index++) {
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if (DynamicSiLibraryPpi->PchGetSataLaneNumByPchId (PCH_LEGACY_ID, Index, &LaneNum) == EFI_SUCCESS) {
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for (Entry = 0; Entry < TableSize; Entry++) {
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if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
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(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) &&
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(PchSetup->SataTopology[Index] == PtssTables[Entry].Topology) &&
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(BoardId == PtssTables[Entry].BoardId)) {
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PtssTableIndex++;
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if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD20) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
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PchPolicy->HsioSataConfig.PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE;
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PchPolicy->HsioSataConfig.PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
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} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_TX_DWORD8)) {
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if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0) {
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PchPolicy->HsioSataConfig.PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE;
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PchPolicy->HsioSataConfig.PortLane[Index].HsioTxGen1DownscaleAmp = (PtssTables[Entry].PtssTable.Value & (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0) >> N_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0;
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}
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if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0) {
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PchPolicy->HsioSataConfig.PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE;
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PchPolicy->HsioSataConfig.PortLane[Index].HsioTxGen2DownscaleAmp = (PtssTables[Entry].PtssTable.Value & (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0) >> N_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0;
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}
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} else {
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DEBUG ((DEBUG_ERROR, "ERROR! PTSS programming: The PTSS table offset and/or mask are not compatible with the BIOS Code.\n"));
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}
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}
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}
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}
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}
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//Case 1a continued: Secondary SATA
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for (Index = 0; Index < MaxsSataPorts; Index++) {
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if (DynamicSiLibraryPpi->PchGetsSataLaneNumByPchId (PCH_LEGACY_ID, Index, &LaneNum) == EFI_SUCCESS) {
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for (Entry = 0; Entry < TableSize; Entry++) {
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if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
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(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) &&
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(PchSetup->sSataTopology[Index] == PtssTables[Entry].Topology) &&
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(BoardId == PtssTables[Entry].BoardId)) {
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PtssTableIndex++;
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if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD20) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
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PchPolicy->HsiosSataConfig.PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE;
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PchPolicy->HsiosSataConfig.PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
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} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_TX_DWORD8)) {
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if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0) {
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PchPolicy->HsiosSataConfig.PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE;
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PchPolicy->HsiosSataConfig.PortLane[Index].HsioTxGen1DownscaleAmp = (PtssTables[Entry].PtssTable.Value & (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0) >> N_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0;
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}
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if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0) {
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PchPolicy->HsiosSataConfig.PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE;
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PchPolicy->HsiosSataConfig.PortLane[Index].HsioTxGen2DownscaleAmp = (PtssTables[Entry].PtssTable.Value & (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0) >> N_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0;
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}
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} else {
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DEBUG ((DEBUG_ERROR, "ERROR! PTSS programming: The PTSS table offset and/or mask are not compatible with the BIOS Code.\n"));
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}
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}
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}
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}
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}
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//Case 1b: PCIe
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for (Index = 0; Index < MaxPciePorts; Index++) {
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if (DynamicSiLibraryPpi->PchGetPcieLaneNumByPchId (PCH_LEGACY_ID, Index, &LaneNum) == EFI_SUCCESS) {
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for (Entry = 0; Entry < TableSize; Entry++) {
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// Skip matching Lanes when the table record has settings for WM20 FIA
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if ((PtssTables[Entry].PtssTable.SbPortID == PID_MODPHY4) ||
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(PtssTables[Entry].PtssTable.SbPortID == PID_MODPHY5)){
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continue;
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}
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if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
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(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
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(PcieTopologyReal[Index] == PtssTables[Entry].Topology) &&
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(BoardId == PtssTables[Entry].BoardId)) {
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PtssTableIndex++;
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if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD25) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
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PchPolicy->HsioPcieConfig.Lane[Index].HsioRxSetCtleEnable = TRUE;
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PchPolicy->HsioPcieConfig.Lane[Index].HsioRxSetCtle = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0;
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}
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else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD39) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0) == (UINT32) B_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0)) {
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PchPolicy->HsioPcieConfig.Lane[Index].HsioIcfgAdjLimitLoEnable = TRUE;
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PchPolicy->HsioPcieConfig.Lane[Index].HsioIcfgAdjLimitLo = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0;
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} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD40) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP) == (UINT32) B_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP)) {
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PchPolicy->HsioPcieConfig.Lane[Index].HsioSampOffstEvenErrSpEnable = TRUE;
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PchPolicy->HsioPcieConfig.Lane[Index].HsioSampOffstEvenErrSp = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP;
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} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD41) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS) == (UINT32) B_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS)) {
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PchPolicy->HsioPcieConfig.Lane[Index].HsioRemainingSamplerOffEnable = TRUE;
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PchPolicy->HsioPcieConfig.Lane[Index].HsioRemainingSamplerOff = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS;
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} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD7) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL) == (UINT32) B_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL)) {
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PchPolicy->HsioPcieConfig.Lane[Index].HsioVgaGainCalEnable = TRUE;
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PchPolicy->HsioPcieConfig.Lane[Index].HsioVgaGainCal = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL;
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} else {
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DEBUG ((DEBUG_ERROR, "ERROR! PTSS programming: The PTSS table offset and/or mask are not compatible with the BIOS Code.\n"));
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}
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}
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}
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}
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}
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//Case 1b Continued: PCIe for WM20 FIA
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for (Index = 0; Index < PCH_MAX_WM20_LANES_NUMBER; Index++) {
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LaneNum = Index;
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for (Entry = 0; Entry < TableSize; Entry++) {
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// Skip entries which are not for WM20 FIA
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if ((PtssTables[Entry].PtssTable.SbPortID != PID_MODPHY4) &&
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(PtssTables[Entry].PtssTable.SbPortID != PID_MODPHY5)){
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continue;
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}
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if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
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(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
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(BoardId == PtssTables[Entry].BoardId)) {
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PtssTableIndex++;
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if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD25) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
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PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioRxSetCtleEnable = TRUE;
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PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioRxSetCtle = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0;
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} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD39) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0) == (UINT32) B_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0)) {
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PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioIcfgAdjLimitLoEnable = TRUE;
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PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioIcfgAdjLimitLo = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0;
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} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD40) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP) == (UINT32) B_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP)) {
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PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioSampOffstEvenErrSpEnable = TRUE;
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PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioSampOffstEvenErrSp = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP;
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} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD41) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS) == (UINT32) B_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS)) {
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PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioRemainingSamplerOffEnable = TRUE;
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PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioRemainingSamplerOff = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS;
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} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD7) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL) == (UINT32) B_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL)) {
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PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioVgaGainCalEnable = TRUE;
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PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioVgaGainCal = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL;
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} else {
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DEBUG ((DEBUG_ERROR, "ERROR! PTSS programming: The PTSS table offset and/or mask are not compatible with the BIOS Code.\n"));
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}
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}
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}
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}
|
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//Case 2: BoardId is unknown, Topology is known/unknown
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if (PtssTableIndex == 0) {
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for (Index = 0; Index < MaxSataPorts; Index++) {
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if (DynamicSiLibraryPpi->PchGetSataLaneNumByPchId (PCH_LEGACY_ID, Index, &LaneNum) == EFI_SUCCESS) {
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for (Entry = 0; Entry < TableSize; Entry++) {
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if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
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(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) &&
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(PchSetup->SataTopology[Index] == PtssTables[Entry].Topology) &&
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(PtssTables[Entry].BoardId == TypePlatformUnknown)) {
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if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD20) &&
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(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
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PchPolicy->HsioSataConfig.PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE;
|
PchPolicy->HsioSataConfig.PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
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} else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_TX_DWORD8) {
|
if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0) {
|
PchPolicy->HsioSataConfig.PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE;
|
PchPolicy->HsioSataConfig.PortLane[Index].HsioTxGen1DownscaleAmp = (PtssTables[Entry].PtssTable.Value & (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0) >> N_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0;
|
}
|
if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0) {
|
PchPolicy->HsioSataConfig.PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE;
|
PchPolicy->HsioSataConfig.PortLane[Index].HsioTxGen2DownscaleAmp = (PtssTables[Entry].PtssTable.Value & (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0) >> N_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0;
|
}
|
} else {
|
DEBUG ((DEBUG_ERROR, "ERROR! PTSS programming: The PTSS table offset and/or mask are not compatible with the BIOS Code.\n"));
|
}
|
}
|
}
|
}
|
}
|
|
// Case 2 Continued secondary SATA when BoardId is unknown, Topology is known/unknown
|
for (Index = 0; Index < MaxsSataPorts; Index++) {
|
if (DynamicSiLibraryPpi->PchGetsSataLaneNumByPchId (PCH_LEGACY_ID, Index, &LaneNum) == EFI_SUCCESS) {
|
for (Entry = 0; Entry < TableSize; Entry++) {
|
if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
|
(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) &&
|
(PchSetup->sSataTopology[Index] == PtssTables[Entry].Topology) &&
|
(PtssTables[Entry].BoardId == TypePlatformUnknown)) {
|
if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD20) &&
|
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
|
PchPolicy->HsiosSataConfig.PortLane[Index].HsioRxGen3EqBoostMagEnable = TRUE;
|
PchPolicy->HsiosSataConfig.PortLane[Index].HsioRxGen3EqBoostMag = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
|
} else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_TX_DWORD8) {
|
if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0) {
|
PchPolicy->HsiosSataConfig.PortLane[Index].HsioTxGen1DownscaleAmpEnable = TRUE;
|
PchPolicy->HsiosSataConfig.PortLane[Index].HsioTxGen1DownscaleAmp = (PtssTables[Entry].PtssTable.Value & (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0) >> N_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0;
|
}
|
if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0) {
|
PchPolicy->HsiosSataConfig.PortLane[Index].HsioTxGen2DownscaleAmpEnable = TRUE;
|
PchPolicy->HsiosSataConfig.PortLane[Index].HsioTxGen2DownscaleAmp = (PtssTables[Entry].PtssTable.Value & (UINT32) B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0) >> N_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0;
|
}
|
}
|
else {
|
DEBUG ((DEBUG_ERROR, "ERROR! PTSS programming: The PTSS table offset and/or mask are not compatible with the BIOS Code.\n"));
|
}
|
}
|
}
|
}
|
}
|
|
for (Index = 0; Index < MaxPciePorts; Index++) {
|
if (DynamicSiLibraryPpi->PchGetPcieLaneNumByPchId (PCH_LEGACY_ID, Index, &LaneNum) == EFI_SUCCESS) {
|
for (Entry = 0; Entry < TableSize; Entry++) {
|
// Skip matching Lanes when the table record has settings for WM20 FIA
|
if ((PtssTables[Entry].PtssTable.SbPortID == PID_MODPHY4) ||
|
(PtssTables[Entry].PtssTable.SbPortID == PID_MODPHY5)){
|
continue;
|
}
|
if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
|
(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
|
(PcieTopologyReal[Index] == PtssTables[Entry].Topology) &&
|
(PtssTables[Entry].BoardId == TypePlatformUnknown)) {
|
if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD25) &&
|
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
|
PchPolicy->HsioPcieConfig.Lane[Index].HsioRxSetCtleEnable = TRUE;
|
PchPolicy->HsioPcieConfig.Lane[Index].HsioRxSetCtle = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0;
|
} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD39) &&
|
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0) == (UINT32) B_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0)) {
|
PchPolicy->HsioPcieConfig.Lane[Index].HsioIcfgAdjLimitLoEnable = TRUE;
|
PchPolicy->HsioPcieConfig.Lane[Index].HsioIcfgAdjLimitLo = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0;
|
} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD40) &&
|
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP) == (UINT32) B_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP)) {
|
PchPolicy->HsioPcieConfig.Lane[Index].HsioSampOffstEvenErrSpEnable = TRUE;
|
PchPolicy->HsioPcieConfig.Lane[Index].HsioSampOffstEvenErrSp = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP;
|
} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD41) &&
|
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS) == (UINT32) B_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS)) {
|
PchPolicy->HsioPcieConfig.Lane[Index].HsioRemainingSamplerOffEnable = TRUE;
|
PchPolicy->HsioPcieConfig.Lane[Index].HsioRemainingSamplerOff = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS;
|
} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD7) &&
|
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL) == (UINT32) B_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL)) {
|
PchPolicy->HsioPcieConfig.Lane[Index].HsioVgaGainCalEnable = TRUE;
|
PchPolicy->HsioPcieConfig.Lane[Index].HsioVgaGainCal = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL;
|
} else {
|
DEBUG ((DEBUG_ERROR, "ERROR! PTSS programming: The PTSS table offset and/or mask are not compatible with the BIOS Code.\n"));
|
}
|
}
|
}
|
}
|
}
|
|
//Continued for PCIe ports in WM20 FIA
|
for (Index = 0; Index < PCH_MAX_WM20_LANES_NUMBER; Index++) {
|
LaneNum = Index;
|
for (Entry = 0; Entry < TableSize; Entry++) {
|
// Skip entries which are not for WM20 FIA
|
if ((PtssTables[Entry].PtssTable.SbPortID != PID_MODPHY4) &&
|
(PtssTables[Entry].PtssTable.SbPortID != PID_MODPHY5)){
|
continue;
|
}
|
if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
|
(PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
|
(PtssTables[Entry].BoardId == TypePlatformUnknown)) {
|
if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD25) &&
|
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
|
PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioRxSetCtleEnable = TRUE;
|
PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioRxSetCtle = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0;
|
} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD39) &&
|
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0) == (UINT32) B_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0)) {
|
PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioIcfgAdjLimitLoEnable = TRUE;
|
PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioIcfgAdjLimitLo = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD39_ICFG_ADJ_LIMITL0;
|
} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD40) &&
|
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP) == (UINT32) B_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP)) {
|
PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioSampOffstEvenErrSpEnable = TRUE;
|
PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioSampOffstEvenErrSp = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD40_SAMP_OFFST_EVEN_ERRSP;
|
} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD41) &&
|
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS) == (UINT32) B_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS)) {
|
PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioRemainingSamplerOffEnable = TRUE;
|
PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioRemainingSamplerOff = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD41_REMAINING_SAMP_OFFSTS;
|
} else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_HSIO_PCR_RX_DWORD7) &&
|
(((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL) == (UINT32) B_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL)) {
|
PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioVgaGainCalEnable = TRUE;
|
PchPolicy->HsioPcieConfigFIAWM20.Lane[Index].HsioVgaGainCal = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_HSIO_PCR_RX_DWORD7_VGA_GAIN_CAL;
|
} else {
|
DEBUG ((DEBUG_ERROR, "ERROR! PTSS programming: The PTSS table offset and/or mask are not compatible with the BIOS Code.\n"));
|
}
|
}
|
}
|
}
|
}
|
}
|
|
PLATFORM_HSIO_PTSS_CONFIG_TABLE PlatformHsioPtssConfigTable =
|
{
|
PLATFORM_HSIO_PTSS_TABLE_SIGNATURE,
|
PLATFORM_HSIO_PTSS_TABLE_VERSION,
|
InstallPlatformHsioPtssTableCallback
|
};
|
|
EFI_STATUS
|
InstallPlatformHsioPtssTableData (
|
IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
|
)
|
{
|
EFI_STATUS Status = EFI_SUCCESS;
|
DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
|
|
Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
|
if (EFI_ERROR (Status)) {
|
ASSERT_EFI_ERROR (Status);
|
return Status;
|
}
|
|
if (DynamicSiLibraryPpi->GetPchSeries() == PchMini) {
|
return Status;
|
}
|
|
Status = UbaConfigPpi->AddData (
|
UbaConfigPpi,
|
&gPlatformHsioPtssTableGuid,
|
&PlatformHsioPtssConfigTable,
|
sizeof(PlatformHsioPtssConfigTable)
|
);
|
|
return Status;
|
}
|
|
