/** @file
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This file is SampleCode of the library for Intel PCH PEI Policy initialzation.
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@copyright
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Copyright 2004 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiPei.h>
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#include "Guid/SetupVariable.h"
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#include <PchSetupVariable.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Ppi/ReadOnlyVariable2.h>
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#include <Library/PeiServicesLib.h>
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#include <PchAccess.h>
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#include <Ppi/PchPolicy.h>
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#include <Register/PchRegsSata.h>
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#include <Library/HobLib.h>
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#include <Platform.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/HobLib.h>
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#include <Guid/GlobalVariable.h>
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#include <Ppi/PchPcieDeviceTable.h>
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#include <Guid/SocketVariable.h>
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#include <Library/PcdLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/UbaUsbOcUpdateLib.h>
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#include <Library/UbaHsioPtssTableConfigLib.h>
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#include <Ppi/DynamicSiLibraryPpi.h>
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//
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// Haddock Creek
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//
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#define DIMM_SMB_SPD_P0C0D0_HC 0xA2
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#define DIMM_SMB_SPD_P0C0D1_HC 0xA0
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#define DIMM_SMB_SPD_P0C1D0_HC 0xA6
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#define DIMM_SMB_SPD_P0C1D1_HC 0xA4
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#define DIMM_SMB_SPD_P0C0D2_HC 0xAA
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#define DIMM_SMB_SPD_P0C1D2_HC 0xA8
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//
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// Sawtooth Peak
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// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only)
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//
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#define DIMM_SMB_SPD_P0C0D0_STP 0xA2
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#define DIMM_SMB_SPD_P0C0D1_STP 0xA0
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#define DIMM_SMB_SPD_P0C1D0_STP 0xA2
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#define DIMM_SMB_SPD_P0C1D1_STP 0xA0
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//
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// Aden Hills
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// DDR4 System (1DPC)
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//
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#define DIMM_SMB_SPD_P0C0D0_AH 0xA0
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#define DIMM_SMB_SPD_P0C0D1_AH 0xA4
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#define DIMM_SMB_SPD_P0C1D0_AH 0xA2
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#define DIMM_SMB_SPD_P0C1D1_AH 0xA6
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusHCRsvdAddresses[] = {
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DIMM_SMB_SPD_P0C0D0_HC,
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DIMM_SMB_SPD_P0C0D1_HC,
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DIMM_SMB_SPD_P0C1D0_HC,
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DIMM_SMB_SPD_P0C1D1_HC
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};
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusSTPRsvdAddresses[] = {
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DIMM_SMB_SPD_P0C0D0_STP,
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DIMM_SMB_SPD_P0C0D1_STP,
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DIMM_SMB_SPD_P0C1D0_STP,
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DIMM_SMB_SPD_P0C1D1_STP
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};
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusAHRsvdAddresses[] = {
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DIMM_SMB_SPD_P0C0D0_AH,
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DIMM_SMB_SPD_P0C0D1_AH,
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DIMM_SMB_SPD_P0C1D0_AH,
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DIMM_SMB_SPD_P0C1D1_AH
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};
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#define PCI_CLASS_NETWORK 0x02
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#define PCI_CLASS_NETWORK_ETHERNET 0x00
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#define PCI_CLASS_NETWORK_OTHER 0x80
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = {
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//
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// Intel PRO/Wireless
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//
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{ 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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//
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// Intel WiMAX/WiFi Link
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//
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{ 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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//
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// Intel Crane Peak WLAN NIC
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//
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{ 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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//
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// Intel Crane Peak w/BT WLAN NIC
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//
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{ 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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//
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// Intel Kelsey Peak WiFi, WiMax
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//
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{ 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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//
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// Intel Centrino Wireless-N 105
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//
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{ 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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//
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// Intel Centrino Wireless-N 135
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//
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{ 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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//
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// Intel Centrino Wireless-N 2200
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//
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{ 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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//
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// Intel Centrino Wireless-N 2230
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//
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{ 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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//
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// Intel Centrino Wireless-N 6235
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//
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{ 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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//
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// Intel CampPeak 2 Wifi
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//
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{ 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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{ 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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//
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// Intel WilkinsPeak 1 Wifi
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//
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{ 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 },
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{ 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 },
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{ 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 },
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{ 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 },
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//
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// Intel Wilkins Peak 2 Wifi
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//
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{ 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 },
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{ 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 },
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{ 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003 },
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{ 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003 },
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//
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// Intel Wilkins Peak PF Wifi
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//
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{ 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0 },
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//
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// End of Table
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//
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{ 0 }
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};
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STATIC
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EFI_STATUS
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InstallPcieDeviceTable (
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IN PCH_PCIE_DEVICE_OVERRIDE *DeviceTable
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)
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{
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EFI_PEI_PPI_DESCRIPTOR *DeviceTablePpiDesc;
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EFI_STATUS Status;
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DeviceTablePpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
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ASSERT (DeviceTablePpiDesc != NULL);
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if (DeviceTablePpiDesc == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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DeviceTablePpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
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DeviceTablePpiDesc->Guid = &gPchPcieDeviceTablePpiGuid;
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DeviceTablePpiDesc->Ppi = DeviceTable;
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Status = PeiServicesInstallPpi (DeviceTablePpiDesc);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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VOID
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UpdatePchUsbConfig (
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IN PCH_USB_CONFIG *PchUsbConfig,
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IN SYSTEM_CONFIGURATION *SetupVariables,
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IN PCH_SETUP *PchRcVariables,
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IN VOID *Usb20OverCurrentMappings,
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IN VOID *Usb30OverCurrentMappings,
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IN VOID *Usb20AfeParams
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);
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static
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VOID
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InstallPlatformVerbTables (
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IN UINTN CodecType
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)
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{
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}
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EFI_STATUS
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EFIAPI
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UpdatePeiPchPolicy (
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IN OUT PCH_POLICY_PPI *PchPolicy
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)
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/*++
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Routine Description:
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This function performs PCH PEI Policy initialzation.
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Arguments:
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PchPolicy The PCH Policy PPI instance
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Returns:
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EFI_SUCCESS The PPI is installed and initialized.
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EFI ERRORS The PPI is not successfully installed.
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EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
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--*/
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{
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UINT8 Index;
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UINTN LpcBaseAddress;
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UINT8 MaxSataPorts;
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UINT8 BmcRootPort;
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UINT8 *SmBusReservedTable;
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UINT8 SmBusReservedNum;
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USB_OVERCURRENT_PIN *Usb20OverCurrentMappings = NULL;
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USB_OVERCURRENT_PIN *Usb30OverCurrentMappings = NULL;
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USB2_PHY_PARAMETERS *Usb20AfeParams = NULL;
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UINT8 VTdSupport;
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SYSTEM_CONFIGURATION *SetupVariables;
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PCH_SETUP *PchRcVariables;
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EFI_STATUS Status = EFI_SUCCESS;
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DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
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DEBUG((DEBUG_INFO, "platform common UpdatePeiPchPolicy entry\n"));
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Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
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if (EFI_ERROR (Status)) {
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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SetupVariables = PcdGetPtr(PcdSetup);
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PchRcVariables = PcdGetPtr(PcdPchSetup);
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LpcBaseAddress = DynamicSiLibraryPpi->MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LPC,
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PCI_FUNCTION_NUMBER_PCH_LPC
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);
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PchPolicy->Port80Route = PchRcVariables->IchPort80Route;
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//
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// DeviceEnables
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//
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if (DynamicSiLibraryPpi->PchIsGbeAvailable ()) {
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PchPolicy->LanConfig.Enable = TRUE;
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PchPolicy->LanConfig.K1OffEnable = PchRcVariables->PchLanK1Off;
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} else {
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PchPolicy->LanConfig.Enable = FALSE;
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}
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PchPolicy->SataConfig.Enable = PchRcVariables->PchSata;
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PchPolicy->sSataConfig.Enable = PchRcVariables->PchsSata;
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PchPolicy->SmbusConfig.Enable = TRUE;
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//
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// CLOCKRUN in LPC has to be disabled:
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// - if a device is connected to LPC0
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// - for LBG A0 stepping
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//
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PchPolicy->PmConfig.PciClockRun = FALSE;
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PchPolicy->PchConfig.Crid = PchRcVariables->PchCrid;
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PchPolicy->PchConfig.Serm = PchRcVariables->PchSerm;
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//
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// SMBUS reserved addresses
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//
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SmBusReservedTable = NULL;
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SmBusReservedNum = 0;
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PchPolicy->SmbusConfig.SmbusIoBase = PCH_SMBUS_BASE_ADDRESS;
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SmBusReservedTable = mSmbusSTPRsvdAddresses;
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SmBusReservedNum = sizeof (mSmbusSTPRsvdAddresses);
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if (SmBusReservedTable != NULL) {
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PchPolicy->SmbusConfig.NumRsvdSmbusAddresses = SmBusReservedNum;
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CopyMem (
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PchPolicy->SmbusConfig.RsvdSmbusAddressTable,
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SmBusReservedTable,
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SmBusReservedNum
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);
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}
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//
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// SATA Config
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//
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PchPolicy->SataConfig.SataMode = PchRcVariables->SataInterfaceMode;
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MaxSataPorts = DynamicSiLibraryPpi->GetPchMaxSataPortNum ();
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for (Index = 0; Index < MaxSataPorts; Index++) {
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if (PchRcVariables->SataTestMode == TRUE)
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{
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PchPolicy->SataConfig.PortSettings[Index].Enable = TRUE;
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} else {
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PchPolicy->SataConfig.PortSettings[Index].Enable = PchRcVariables->SataPort[Index];
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}
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PchPolicy->SataConfig.PortSettings[Index].HotPlug = PchRcVariables->SataHotPlug[Index];
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PchPolicy->SataConfig.PortSettings[Index].SpinUp = PchRcVariables->SataSpinUp[Index];
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PchPolicy->SataConfig.PortSettings[Index].External = PchRcVariables->SataExternal[Index];
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PchPolicy->SataConfig.PortSettings[Index].InterlockSw = PchRcVariables->SataMechanicalSw[Index];
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PchPolicy->SataConfig.PortSettings[Index].DevSlp = PchRcVariables->PxDevSlp[Index];
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PchPolicy->SataConfig.PortSettings[Index].EnableDitoConfig = PchRcVariables->EnableDitoConfig[Index];
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PchPolicy->SataConfig.PortSettings[Index].DmVal = PchRcVariables->DmVal[Index];
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PchPolicy->SataConfig.PortSettings[Index].DitoVal = PchRcVariables->DitoVal[Index];
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PchPolicy->SataConfig.PortSettings[Index].SolidStateDrive = PchRcVariables->SataType[Index];
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}
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if (PchPolicy->SataConfig.SataMode == PchSataModeRaid) {
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PchPolicy->SataConfig.Rst.RaidAlternateId = PchRcVariables->SataAlternateId;
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PchPolicy->SataConfig.Rst.EfiRaidDriverLoad = PchRcVariables->SataRaidLoadEfiDriver[0];
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}
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PchPolicy->SataConfig.Rst.Raid0 = PchRcVariables->SataRaidR0;
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PchPolicy->SataConfig.Rst.Raid1 = PchRcVariables->SataRaidR1;
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PchPolicy->SataConfig.Rst.Raid10 = PchRcVariables->SataRaidR10;
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PchPolicy->SataConfig.Rst.Raid5 = PchRcVariables->SataRaidR5;
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PchPolicy->SataConfig.Rst.Irrt = PchRcVariables->SataRaidIrrt;
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PchPolicy->SataConfig.Rst.OromUiBanner = PchRcVariables->SataRaidOub;
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PchPolicy->SataConfig.Rst.HddUnlock = PchRcVariables->SataHddlk;
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PchPolicy->SataConfig.Rst.LedLocate = PchRcVariables->SataLedl;
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PchPolicy->SataConfig.Rst.IrrtOnly = PchRcVariables->SataRaidIooe;
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PchPolicy->SataConfig.Rst.SmartStorage = PchRcVariables->SataRaidSrt;
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PchPolicy->SataConfig.Rst.OromUiDelay = PchRcVariables->SataRaidOromDelay;
|
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PchPolicy->SataConfig.EnclosureSupport = TRUE;
|
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PchPolicy->SataConfig.SalpSupport = PchRcVariables->SataSalp;
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PchPolicy->SataConfig.TestMode = PchRcVariables->SataTestMode;
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for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) {
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if ((PchRcVariables->PchSata == TRUE) && (PchRcVariables->SataInterfaceMode == PchSataModeRaid)) {
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PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = PchRcVariables->RstPcieStorageRemap[Index];
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PchPolicy->SataConfig.RstPcieStorageRemap[Index].RstPcieStoragePort = PchRcVariables->RstPcieStorageRemapPort[Index];
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} else {
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PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = FALSE;
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}
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}
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//
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// sSATA Config
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//
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PchPolicy->sSataConfig.SataMode = PchRcVariables->sSataInterfaceMode;
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MaxSataPorts = DynamicSiLibraryPpi->GetPchMaxsSataPortNum ();
|
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for (Index = 0; Index < MaxSataPorts; Index++) {
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if (PchRcVariables->sSataTestMode == TRUE)
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{
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PchPolicy->sSataConfig.PortSettings[Index].Enable = TRUE;
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} else {
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PchPolicy->sSataConfig.PortSettings[Index].Enable = PchRcVariables->sSataPort[Index];
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}
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PchPolicy->sSataConfig.PortSettings[Index].HotPlug = PchRcVariables->sSataHotPlug[Index];
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PchPolicy->sSataConfig.PortSettings[Index].SpinUp = PchRcVariables->sSataSpinUp[Index];
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PchPolicy->sSataConfig.PortSettings[Index].External = PchRcVariables->sSataExternal[Index];
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PchPolicy->sSataConfig.PortSettings[Index].DevSlp = PchRcVariables->sPxDevSlp[Index];
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PchPolicy->sSataConfig.PortSettings[Index].EnableDitoConfig = PchRcVariables->sEnableDitoConfig[Index];
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PchPolicy->sSataConfig.PortSettings[Index].DmVal = PchRcVariables->sDmVal[Index];
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PchPolicy->sSataConfig.PortSettings[Index].DitoVal = PchRcVariables->sDitoVal[Index];
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PchPolicy->sSataConfig.PortSettings[Index].SolidStateDrive = PchRcVariables->sSataType[Index];
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}
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if (PchPolicy->sSataConfig.SataMode == PchSataModeRaid) {
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PchPolicy->sSataConfig.Rst.RaidAlternateId = PchRcVariables->sSataAlternateId;
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PchPolicy->sSataConfig.Rst.EfiRaidDriverLoad = PchRcVariables->SataRaidLoadEfiDriver[1];
|
}
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PchPolicy->sSataConfig.Rst.Raid0 = PchRcVariables->sSataRaidR0;
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PchPolicy->sSataConfig.Rst.Raid1 = PchRcVariables->sSataRaidR1;
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PchPolicy->sSataConfig.Rst.Raid10 = PchRcVariables->sSataRaidR10;
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PchPolicy->sSataConfig.Rst.Raid5 = PchRcVariables->sSataRaidR5;
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PchPolicy->sSataConfig.Rst.Irrt = PchRcVariables->sSataRaidIrrt;
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PchPolicy->sSataConfig.Rst.OromUiBanner = PchRcVariables->sSataRaidOub;
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PchPolicy->sSataConfig.Rst.HddUnlock = PchRcVariables->sSataHddlk;
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PchPolicy->sSataConfig.Rst.LedLocate = PchRcVariables->sSataLedl;
|
PchPolicy->sSataConfig.Rst.IrrtOnly = PchRcVariables->sSataRaidIooe;
|
PchPolicy->sSataConfig.Rst.SmartStorage = PchRcVariables->sSataRaidSrt;
|
PchPolicy->sSataConfig.Rst.OromUiDelay = PchRcVariables->sSataRaidOromDelay;
|
|
PchPolicy->sSataConfig.EnclosureSupport = TRUE;
|
|
PchPolicy->sSataConfig.SalpSupport = PchRcVariables->sSataSalp;
|
PchPolicy->sSataConfig.TestMode = PchRcVariables->sSataTestMode;
|
//
|
// Initiate DMI Configuration
|
//
|
if (SetupVariables->PcieDmiAspm != PLATFORM_POR) {
|
if (SetupVariables->PcieDmiAspm != 0xFF) {
|
PchPolicy->DmiConfig.DmiAspm = TRUE;
|
} else {
|
PchPolicy->DmiConfig.DmiAspm = FALSE;
|
}
|
}
|
DEBUG((DEBUG_ERROR, "PchPolicy->DmiConfig.DmiAspm =%x\n", PchPolicy->DmiConfig.DmiAspm));
|
//
|
// PCI express config
|
//
|
PchPolicy->PcieConfig.DisableRootPortClockGating = SetupVariables->PcieClockGatingDisabled;
|
PchPolicy->PcieConfig.EnablePort8xhDecode = PchRcVariables->PcieRootPort8xhDecode;
|
PchPolicy->PcieConfig.PchPciePort8xhDecodePortIndex = PchRcVariables->Pcie8xhDecodePortIndex;
|
PchPolicy->PcieConfig.EnablePeerMemoryWrite = PchRcVariables->PcieRootPortPeerMemoryWriteEnable;
|
PchPolicy->PcieConfig.ComplianceTestMode = PchRcVariables->PcieComplianceTestMode;
|
|
///
|
/// Temporary WA: Force Link speed on BMC board to GEN1
|
/// TODO: remove this WA together with Purley platforms support
|
///
|
BmcRootPort = PcdGet8 (PcdOemSkuBmcPciePortNumber);
|
if ((BmcRootPort != 0xFF) && (BmcRootPort < ARRAY_SIZE(PchRcVariables->PcieRootPortSpeed))) {
|
DEBUG ((DEBUG_INFO, "WA Force Link Speed to GEN1: PciePort: %d", BmcRootPort));
|
PchRcVariables->PcieRootPortSpeed[BmcRootPort] = 1;
|
}
|
for (Index = 0; Index < DynamicSiLibraryPpi->GetPchMaxPciePortNum (); Index++) {
|
PchPolicy->PcieConfig.RootPort[Index].Enable = PchRcVariables->PcieRootPortEn[Index];
|
PchPolicy->PcieConfig.RootPort[Index].PhysicalSlotNumber = (UINT8) Index;
|
if (PchRcVariables->PchPcieGlobalAspm > PchPcieAspmDisabled) {
|
// Disabled a.k.a. Per individual port
|
PchPolicy->PcieConfig.RootPort[Index].Aspm = PchRcVariables->PchPcieGlobalAspm;
|
} else {
|
PchPolicy->PcieConfig.RootPort[Index].Aspm = PchRcVariables->PcieRootPortAspm[Index];
|
}
|
PchPolicy->PcieConfig.RootPort[Index].L1Substates = PchRcVariables->PcieRootPortL1SubStates[Index];
|
PchPolicy->PcieConfig.RootPort[Index].AcsEnabled = PchRcVariables->PcieRootPortACS[Index];
|
PchPolicy->PcieConfig.RootPort[Index].PmSci = PchRcVariables->PcieRootPortPMCE[Index];
|
PchPolicy->PcieConfig.RootPort[Index].HotPlug = PchRcVariables->PcieRootPortHPE[Index];
|
PchPolicy->PcieConfig.RootPort[Index].AdvancedErrorReporting = PchRcVariables->PcieRootPortAER[Index];
|
PchPolicy->PcieConfig.RootPort[Index].UnsupportedRequestReport = PchRcVariables->PcieRootPortURE[Index];
|
PchPolicy->PcieConfig.RootPort[Index].FatalErrorReport = PchRcVariables->PcieRootPortFEE[Index];
|
PchPolicy->PcieConfig.RootPort[Index].NoFatalErrorReport = PchRcVariables->PcieRootPortNFE[Index];
|
PchPolicy->PcieConfig.RootPort[Index].CorrectableErrorReport = PchRcVariables->PcieRootPortCEE[Index];
|
PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnFatalError = PchRcVariables->PcieRootPortSFE[Index];
|
PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnNonFatalError = PchRcVariables->PcieRootPortSNE[Index];
|
PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnCorrectableError = PchRcVariables->PcieRootPortSCE[Index];
|
PchPolicy->PcieConfig.RootPort[Index].TransmitterHalfSwing = PchRcVariables->PcieRootPortTHS[Index];
|
PchPolicy->PcieConfig.RootPort[Index].CompletionTimeout = PchRcVariables->PcieRootPortCompletionTimeout[Index];
|
PchPolicy->PcieConfig.RootPort[Index].PcieSpeed = PchRcVariables->PcieRootPortSpeed[Index];
|
|
PchPolicy->PcieConfig.RootPort[Index].MaxPayload = PchRcVariables->PcieRootPortMaxPayLoadSize[Index];
|
PchPolicy->PcieConfig.RootPort[Index].Gen3EqPh3Method = PchRcVariables->PcieRootPortEqPh3Method[Index];
|
PchPolicy->PcieConfig.RootPort[Index].SlotImplemented = TRUE;
|
}
|
PchPolicy->PcieConfig.RootPort[BmcRootPort].SlotImplemented = FALSE;
|
|
for (Index = 0; Index < DynamicSiLibraryPpi->GetPchMaxPciePortNum (); ++Index) {
|
PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cm = PchRcVariables->PcieLaneCm[Index];
|
PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cp = PchRcVariables->PcieLaneCp[Index];
|
}
|
if (PchRcVariables->PcieSwEqOverride) {
|
for (Index = 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index++) {
|
PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cm = PchRcVariables->PcieSwEqCoeffCm[Index];
|
PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cp = PchRcVariables->PcieSwEqCoeffCp[Index];
|
}
|
}
|
|
PchPolicy->PcieConfig.MaxReadRequestSize = PchRcVariables->PcieRootPortMaxReadRequestSize;
|
///
|
/// Update Competion Timeout settings for Upling ports for Server PCH
|
///
|
PchPolicy->PcieConfig.PchPcieUX16CompletionTimeout = PchRcVariables->PchPcieUX16CompletionTimeout;
|
PchPolicy->PcieConfig.PchPcieUX8CompletionTimeout = PchRcVariables->PchPcieUX8CompletionTimeout;
|
///
|
/// Update Max Payload Size settings for Upling ports for Server PCH
|
///
|
PchPolicy->PcieConfig.PchPcieUX16MaxPayload = PchRcVariables->PchPcieUX16MaxPayloadSize;
|
PchPolicy->PcieConfig.PchPcieUX8MaxPayload = PchRcVariables->PchPcieUX8MaxPayloadSize;
|
CopyMem (&VTdSupport, (UINT8 *)PcdGetPtr(PcdSocketIioConfig) + OFFSET_OF(SOCKET_IIO_CONFIGURATION, VTdSupport), sizeof(VTdSupport));
|
PchPolicy->PcieConfig.VTdSupport = VTdSupport;
|
if (DynamicSiLibraryPpi->X2ApicIdDetect (NULL)) {
|
PchPolicy->PcieConfig.VTdSupport = TRUE;
|
}
|
///
|
/// Assign ClkReq signal to root port. (Base 0)
|
/// For LP, Set 0 - 5
|
/// For H, Set 0 - 15
|
/// Note that if GbE is enabled, ClkReq assigned to GbE will not be available for Root Port. (TODO for Purley)
|
///
|
//
|
// HdAudioConfig
|
//
|
PchPolicy->HdAudioConfig.Enable = PchRcVariables->PchHdAudio;
|
PchPolicy->HdAudioConfig.DspEnable = FALSE;
|
PchPolicy->HdAudioConfig.Pme = PchRcVariables->PchHdAudioPme;
|
PchPolicy->HdAudioConfig.IoBufferOwnership = PchRcVariables->PchHdAudioIoBufferOwnership;
|
PchPolicy->HdAudioConfig.IoBufferVoltage = PchRcVariables->PchHdAudioIoBufferVoltage;
|
PchPolicy->HdAudioConfig.ResetWaitTimer = 300;
|
PchPolicy->HdAudioConfig.IDispCodecDisconnect = TRUE; //iDisp is permanently disabled
|
for(Index = 0; Index < HDAUDIO_FEATURES; Index++) {
|
PchPolicy->HdAudioConfig.DspFeatureMask |= (UINT32)(PchRcVariables->PchHdAudioFeature[Index] ? (1 << Index) : 0);
|
}
|
|
for(Index = 0; Index < HDAUDIO_PP_MODULES; Index++) {
|
PchPolicy->HdAudioConfig.DspPpModuleMask |= (UINT32)(PchRcVariables->PchHdAudioPostProcessingMod[Index] ? (1 << Index) : 0);
|
}
|
|
if (PchPolicy->HdAudioConfig.Enable) {
|
InstallPlatformVerbTables (PchRcVariables->PchHdAudioCodecSelect);
|
}
|
|
PchPolicy->HdAudioConfig.VcType = PchRcVariables->DfxHdaVcType;
|
//
|
// LockDown
|
//
|
|
|
PchPolicy->LockDownConfig.RtcLock = PchRcVariables->PchRtcLock;
|
PchPolicy->LockDownConfig.SpiEiss = TRUE;
|
PchPolicy->LockDownConfig.GlobalSmi = TRUE;
|
PchPolicy->LockDownConfig.BiosInterface = TRUE;
|
PchPolicy->LockDownConfig.GpioLockDown = PchRcVariables->PchGpioLockDown;
|
PchPolicy->LockDownConfig.TcoLock = TRUE;
|
|
if(PchRcVariables->PchP2sbUnlock) {
|
PchPolicy->P2sbConfig.SbiUnlock = TRUE;
|
PchPolicy->P2sbConfig.PsfUnlock = TRUE;
|
} else {
|
PchPolicy->P2sbConfig.SbiUnlock = FALSE;
|
PchPolicy->P2sbConfig.PsfUnlock = FALSE;
|
}
|
PchPolicy->P2sbConfig.P2SbReveal = PchRcVariables->PchP2sbDevReveal;
|
|
//
|
// Update SPI policies
|
//
|
PchPolicy->SpiConfig.ShowSpiController = TRUE;
|
|
PchPolicy->PmConfig.PmcReadDisable = TRUE;
|
|
if (PchRcVariables->PchAdrEn != PLATFORM_POR) {
|
PchPolicy->AdrConfig.PchAdrEn = PchRcVariables->PchAdrEn;
|
}
|
PchPolicy->AdrConfig.AdrGpioSel = PchRcVariables->AdrGpioSel;
|
if (PchRcVariables->AdrHostPartitionReset != PLATFORM_POR) {
|
PchPolicy->AdrConfig.AdrHostPartitionReset = PchRcVariables->AdrHostPartitionReset;
|
}
|
if (PchRcVariables->AdrTimerEn != PLATFORM_POR) {
|
PchPolicy->AdrConfig.AdrTimerEn = PchRcVariables->AdrTimerEn;
|
}
|
if (PchRcVariables->AdrTimerVal != ADR_TMR_SETUP_DEFAULT_POR) {
|
PchPolicy->AdrConfig.AdrTimerVal = PchRcVariables->AdrTimerVal;
|
}
|
if (PchRcVariables->AdrMultiplierVal != ADR_MULT_SETUP_DEFAULT_POR) {
|
PchPolicy->AdrConfig.AdrMultiplierVal = PchRcVariables->AdrMultiplierVal;
|
}
|
|
//
|
// Thermal Config
|
//
|
if ((PchRcVariables->MemoryThermalManagement != FALSE) &&
|
((PchRcVariables->ExttsViaTsOnBoard != FALSE) || (PchRcVariables->ExttsViaTsOnDimm != FALSE)))
|
{
|
PchPolicy->ThermalConfig.MemoryThrottling.Enable = TRUE;
|
PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].PmsyncEnable = TRUE;
|
PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].PmsyncEnable = TRUE;
|
PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].C0TransmitEnable = TRUE;
|
PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].C0TransmitEnable = TRUE;
|
PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].PinSelection = 1;
|
PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].PinSelection = 0;
|
} else {
|
PchPolicy->ThermalConfig.MemoryThrottling.Enable = FALSE;
|
}
|
|
//
|
// IOAPIC Config
|
//
|
PchPolicy->IoApicConfig.IoApicEntry24_119 = PchRcVariables->PchIoApic24119Entries;
|
PchPolicy->IoApicConfig.BdfValid = 1;
|
PchPolicy->IoApicConfig.BusNumber = PCI_BUS_NUMBER_PCH_IOAPIC;
|
PchPolicy->IoApicConfig.DeviceNumber = PCI_DEVICE_NUMBER_PCH_IOAPIC;
|
PchPolicy->IoApicConfig.FunctionNumber = PCI_FUNCTION_NUMBER_PCH_IOAPIC;
|
|
PchPolicy->HpetConfig.BdfValid = 1;
|
PchPolicy->HpetConfig.BusNumber = PCI_BUS_NUMBER_PCH_HPET;
|
PchPolicy->HpetConfig.DeviceNumber = PCI_DEVICE_NUMBER_PCH_HPET;
|
PchPolicy->HpetConfig.FunctionNumber = PCI_FUNCTION_NUMBER_PCH_HPET0;
|
|
PchPolicy->PchInterruptConfig.ShutdownPolicySelect = PchRcVariables->ShutdownPolicySelect;
|
//
|
// Misc PM Config
|
//
|
PchPolicy->PmConfig.PchDeepSxPol = PchRcVariables->DeepSxMode;
|
PchPolicy->PmConfig.WakeConfig.WolEnableOverride = PchRcVariables->PchWakeOnLan;
|
PchPolicy->PmConfig.WakeConfig.WoWlanEnable = PchRcVariables->PchWakeOnWlan;
|
PchPolicy->PmConfig.WakeConfig.WoWlanDeepSxEnable = PchRcVariables->PchWakeOnWlanDeepSx;
|
PchPolicy->PmConfig.WakeConfig.Gp27WakeFromDeepSx = PchRcVariables->Gp27WakeFromDeepSx;
|
PchPolicy->PmConfig.SlpLanLowDc = PchRcVariables->PchSlpLanLowDc;
|
PchPolicy->PmConfig.PowerResetStatusClear.MeWakeSts = TRUE;
|
PchPolicy->PmConfig.PowerResetStatusClear.MeHrstColdSts = TRUE;
|
PchPolicy->PmConfig.PowerResetStatusClear.MeHrstWarmSts = TRUE;
|
PchPolicy->PmConfig.PciePllSsc = PchRcVariables->PciePllSsc;
|
PchPolicy->PmConfig.Dwr_BmcRootPort = PchRcVariables->Dwr_BmcRootPort;
|
|
PchPolicy->PmConfig.PchGbl2HostEn.Bits.PMCGBL = PchRcVariables->DwrEn_PMCGBL;
|
PchPolicy->PmConfig.PchGbl2HostEn.Bits.MEWDT = PchRcVariables->DwrEn_MEWDT;
|
PchPolicy->PmConfig.PchGbl2HostEn.Bits.IEWDT = PchRcVariables->DwrEn_IEWDT;
|
|
//
|
// DefaultSvidSid Config
|
//
|
PchPolicy->PchConfig.SubSystemVendorId = V_PCH_INTEL_VENDOR_ID;
|
PchPolicy->PchConfig.SubSystemId = V_PCH_DEFAULT_SID;
|
PchPolicy->PchConfig.EnableClockSpreadSpec = PchRcVariables->EnableClockSpreadSpec;
|
//
|
// Thermal Config
|
//
|
PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = PchRcVariables->PchCrossThrottling;
|
PchPolicy->ThermalConfig.ThermalThrottling.DmiHaAWC.SuggestedSetting = TRUE;
|
if (PchRcVariables->ThermalDeviceEnable == PchThermalDeviceAuto) {
|
PchPolicy->ThermalConfig.ThermalDeviceEnable = PchThermalDeviceEnabledPci;
|
} else {
|
PchPolicy->ThermalConfig.ThermalDeviceEnable = PchRcVariables->ThermalDeviceEnable;
|
}
|
|
PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.SuggestedSetting = TRUE;
|
PchPolicy->ThermalConfig.ThermalThrottling.SataTT.SuggestedSetting = TRUE;
|
PchPolicy->ThermalConfig.ThermalThrottling.sSataTT.SuggestedSetting = TRUE;
|
|
///
|
///Set PCHHOT# to 85C.
|
///
|
PchPolicy->ThermalConfig.PchHotLevel = 0x10E;
|
|
// DCI (EXI)
|
//
|
PchPolicy->DciConfig.DciEn = DCI_DISABLE;
|
PchPolicy->DciConfig.DciAutoDetect = DCI_DISABLE;
|
|
//
|
// Initialize Serial IRQ Config
|
//
|
PchPolicy->SerialIrqConfig.SirqEnable = TRUE;
|
PchPolicy->SerialIrqConfig.StartFramePulse = PchSfpw4Clk;
|
if (PchRcVariables->PchSirqMode == 0) {
|
PchPolicy->SerialIrqConfig.SirqMode = PchQuietMode;
|
} else {
|
PchPolicy->SerialIrqConfig.SirqMode = PchContinuousMode;
|
}
|
|
//
|
// Port 61h emulation
|
//
|
PchPolicy->Port61hSmmConfig.Enable = TRUE;
|
|
//
|
// DMI configuration
|
//
|
PchPolicy->DmiConfig.DmiLinkDownHangBypass = PchRcVariables->DmiLinkDownHangBypass;
|
PchPolicy->DmiConfig.DmiStopAndScreamEnable = PchRcVariables->PcieDmiStopAndScreamEnable;
|
|
//
|
// Update Pch Usb Config
|
//
|
PlatformGetUsbOcMappings (
|
(USB_OVERCURRENT_PIN **) &Usb20OverCurrentMappings,
|
(USB_OVERCURRENT_PIN **) &Usb30OverCurrentMappings,
|
(USB2_PHY_PARAMETERS **) &Usb20AfeParams
|
);
|
UpdatePchUsbConfig (
|
&PchPolicy->UsbConfig,
|
SetupVariables,
|
PchRcVariables,
|
Usb20OverCurrentMappings,
|
Usb30OverCurrentMappings,
|
Usb20AfeParams
|
);
|
|
//
|
// Install PCIe device override table
|
//
|
InstallPcieDeviceTable (mPcieDeviceTable);
|
|
//
|
// Initialize PTSS board specyfic HSIO settings
|
//
|
InstallPlatformHsioPtssTable (PchRcVariables, PchPolicy);
|
|
|
PchPolicy->PchTraceHubConfig.PchTraceHubHide = TRUE;
|
return EFI_SUCCESS;
|
}
|
|
|
/**
|
Performs silicon pre-mem policy update.
|
|
The meaning of Policy is defined by silicon code.
|
It could be the raw data, a handle, a PPI, etc.
|
|
The input Policy must be returned by SiliconPolicyDonePreMem().
|
|
1) In FSP path, the input Policy should be FspmUpd.
|
A platform may use this API to update the FSPM UPD policy initialized
|
by the silicon module or the default UPD data.
|
The output of FSPM UPD data from this API is the final UPD data.
|
|
2) In non-FSP path, the board may use additional way to get
|
the silicon policy data field based upon the input Policy.
|
|
@param[in, out] Policy Pointer to policy.
|
|
@return the updated policy.
|
**/
|
VOID *
|
EFIAPI
|
SiliconPolicyUpdatePreMem (
|
IN OUT VOID *Policy
|
)
|
{
|
UpdatePeiPchPolicy (Policy);
|
return Policy;
|
}
|
|
/**
|
Performs silicon post-mem policy update.
|
|
The meaning of Policy is defined by silicon code.
|
It could be the raw data, a handle, a PPI, etc.
|
|
The input Policy must be returned by SiliconPolicyDonePostMem().
|
|
1) In FSP path, the input Policy should be FspsUpd.
|
A platform may use this API to update the FSPS UPD policy initialized
|
by the silicon module or the default UPD data.
|
The output of FSPS UPD data from this API is the final UPD data.
|
|
2) In non-FSP path, the board may use additional way to get
|
the silicon policy data field based upon the input Policy.
|
|
@param[in, out] Policy Pointer to policy.
|
|
@return the updated policy.
|
**/
|
VOID *
|
EFIAPI
|
SiliconPolicyUpdatePostMem (
|
IN OUT VOID *Policy
|
)
|
{
|
return Policy;
|
}
|
