/** @file
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Platform Hook Library instances
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@copyright
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Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <PiPei.h>
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#include <Platform.h>
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#include <Guid/SetupVariable.h>
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#include <Guid/SocketVariable.h>
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#include <PchSetupVariable.h>
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#include <Register/PchRegsPmc.h>
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#include <Ppi/FirmwareVolumeInfo.h>
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#include <Ppi/ReadOnlyVariable2.h>
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#include <Ppi/DynamicSiLibraryPpi.h>
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#include <Guid/GlobalVariable.h>
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#include <Guid/PlatformInfo.h>
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#include <Guid/FirmwareFileSystem3.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/PeiPlatformHooklib.h>
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#include <Library/ReportStatusCodeLib.h>
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#include <Library/PeiServicesTablePointerLib.h>
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#include <Library/BaseLib.h>
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#include <Library/IoLib.h>
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#include <Library/HobLib.h>
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#include <Library/BoardInitLib.h>
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#include <Library/PcdLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <SioRegs.h>
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EFI_STATUS
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UpdatePlatformInfo (
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IN SYSTEM_CONFIGURATION *SystemConfiguration,
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IN SOCKET_PROCESSORCORE_CONFIGURATION *SocketProcessorCoreConfig,
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IN SOCKET_IIO_CONFIGURATION *SocketIioConfig
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);
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EFI_STATUS
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EFIAPI
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BoardDetect (
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VOID
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)
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{
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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BoardDebugInit (
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VOID
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)
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{
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return EFI_SUCCESS;
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}
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EFI_BOOT_MODE
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EFIAPI
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BoardBootModeDetect (
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VOID
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)
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{
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return BOOT_WITH_FULL_CONFIGURATION;
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}
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VOID
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EarlyPlatformPchInit (
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VOID
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)
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{
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UINT16 Data16;
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UINT8 Data8;
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UINTN LpcBaseAddress;
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UINT8 TcoRebootHappened;
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UINTN SpiBaseAddress;
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UINTN P2sbBase;
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EFI_STATUS Status = EFI_SUCCESS;
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DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
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DEBUG((DEBUG_INFO, "EarlyPlatformPchInit - Start\n"));
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Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
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if (EFI_ERROR (Status)) {
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ASSERT_EFI_ERROR (Status);
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return;
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}
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LpcBaseAddress = DynamicSiLibraryPpi->MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LPC,
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PCI_FUNCTION_NUMBER_PCH_LPC
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);
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SpiBaseAddress = DynamicSiLibraryPpi->MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_SPI,
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PCI_FUNCTION_NUMBER_PCH_SPI
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);
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//
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// Program bar
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//
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P2sbBase = DynamicSiLibraryPpi->MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_P2SB,
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PCI_FUNCTION_NUMBER_PCH_P2SB
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);
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MmioWrite32 (P2sbBase + R_P2SB_CFG_SBREG_BAR, PCH_PCR_BASE_ADDRESS);
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MmioOr8 (P2sbBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
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//
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// LPC I/O Configuration
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//
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DynamicSiLibraryPpi->PchLpcIoDecodeRangesSet (
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(V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) |
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(V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) |
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(V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)
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);
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DynamicSiLibraryPpi->PchLpcIoEnableDecodingSet (
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B_LPC_CFG_IOE_ME2 |
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B_LPC_CFG_IOE_SE |
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B_LPC_CFG_IOE_ME1 |
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B_LPC_CFG_IOE_KE |
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B_LPC_CFG_IOE_HGE |
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B_LPC_CFG_IOE_LGE |
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B_LPC_CFG_IOE_FDE |
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B_LPC_CFG_IOE_PPE |
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B_LPC_CFG_IOE_CBE |
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B_LPC_CFG_IOE_CAE
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);
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//
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// Enable the upper 128-byte bank of RTC RAM
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//
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DynamicSiLibraryPpi->PchPcrAndThenOr32 (PID_RTC_HOST, R_RTC_PCR_CONF, (UINT32)~0, B_RTC_PCR_CONF_UCMOS_EN);
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//
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// Disable the Watchdog timer expiration from causing a system reset
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//
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DynamicSiLibraryPpi->PchPcrAndThenOr32 (PID_ITSS, R_ITSS_PCR_GIC, (UINT32)~0, B_ITSS_PCR_GIC_AME);
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//
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// Halt the TCO timer
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//
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Data16 = IoRead16 (PCH_TCO_BASE_ADDRESS + R_TCO_IO_TCO1_CNT);
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Data16 |= B_TCO_IO_TCO1_CNT_TMR_HLT;
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IoWrite16 (PCH_TCO_BASE_ADDRESS + R_TCO_IO_TCO1_CNT, Data16);
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//
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// Read the Second TO status bit
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//
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Data8 = IoRead8 (PCH_TCO_BASE_ADDRESS + R_TCO_IO_TCO2_STS);
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if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) == B_TCO_IO_TCO2_STS_SECOND_TO) {
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TcoRebootHappened = 1;
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DEBUG ((EFI_D_INFO, "EarlyPlatformPchInit - TCO Second TO status bit is set. This might be a TCO reboot\n"));
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} else {
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TcoRebootHappened = 0;
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}
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//
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// Clear the Second TO status bit
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//
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Data8 |= (UINT8) B_TCO_IO_TCO2_STS_SECOND_TO;
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Data8 &= (UINT8) ~B_TCO_IO_TCO2_STS_INTRD_DET;
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IoWrite8 (PCH_TCO_BASE_ADDRESS + R_TCO_IO_TCO2_STS, Data8);
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//
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// Disable SERR NMI and IOCHK# NMI in port 61
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//
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Data8 = IoRead8 (R_PCH_IO_NMI_SC);
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Data8 |= (B_PCH_IO_NMI_SC_PCI_SERR_EN | B_PCH_IO_NMI_SC_IOCHK_NMI_EN);
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IoWrite8 (R_PCH_IO_NMI_SC, Data8);
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DynamicSiLibraryPpi->PchPcrAndThenOr32 (PID_ITSS, R_ITSS_PCR_GIC, (UINT32)~B_ITSS_PCR_GIC_AME, 0);
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//
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// Clear EISS bit to allow for SPI use
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//
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MmioAnd8 (SpiBaseAddress + R_SPI_CFG_BC, (UINT8)~B_SPI_CFG_BC_EISS);
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//
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// Enable LPC decode at 0xCA0 for BMC
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//
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DynamicSiLibraryPpi->PchLpcGenIoRangeSet ((IPMI_DEFAULT_SMM_IO_BASE & 0xFF0), 0x10);
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DEBUG ((EFI_D_INFO, "[IPMI_DEBUG]: PchLpcGenIoRangeSet 0x%x!\n", IPMI_DEFAULT_SMM_IO_BASE));
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DEBUG((DEBUG_INFO, "EarlyPlatformPchInit - End\n"));
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}
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EFI_STATUS
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EFIAPI
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BoardInitBeforeMemoryInit (
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VOID
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)
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{
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SYSTEM_CONFIGURATION SysSetupData;
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SOCKET_PROCESSORCORE_CONFIGURATION SocketProcessorCoreSetupData;
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SOCKET_IIO_CONFIGURATION SocketIioSetupData;
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PCH_SETUP PchSetupData;
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UINT16 ABase;
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UINT16 Pm1Sts = 0;
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UINT32 Pm1Cnt;
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EFI_STATUS Status;
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DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
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Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
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if (EFI_ERROR (Status)) {
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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//
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// Get Setup Data
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//
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ZeroMem (&SysSetupData, sizeof(SYSTEM_CONFIGURATION));
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ZeroMem (&SocketProcessorCoreSetupData, sizeof(SOCKET_PROCESSORCORE_CONFIGURATION));
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ZeroMem (&SocketIioSetupData, sizeof(SOCKET_IIO_CONFIGURATION));
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ZeroMem (&PchSetupData, sizeof(PCH_SETUP));
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CopyMem (&PchSetupData, PcdGetPtr(PcdPchSetup), sizeof(PCH_SETUP));
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CopyMem (&SysSetupData, PcdGetPtr(PcdSetup), sizeof(SYSTEM_CONFIGURATION));
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CopyMem (&SocketProcessorCoreSetupData, PcdGetPtr(PcdSocketProcessorCoreConfig), sizeof(SOCKET_PROCESSORCORE_CONFIGURATION));
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CopyMem (&SocketIioSetupData, PcdGetPtr(PcdSocketIioConfig), sizeof(SOCKET_IIO_CONFIGURATION));
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//
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// Configure GPIO
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//
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Status = BoardInit ();
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EarlyPlatformPchInit ();
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///
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/// Set what state (S0/S5) to go to when power is re-applied after a power failure (G3 state)
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///
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DynamicSiLibraryPpi->PmcSetPlatformStateAfterPowerFailure (PchSetupData.StateAfterG3);
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//
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// Check PWR FLR
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//
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if (DynamicSiLibraryPpi->PmcIsPowerFailureDetected ()) {
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DynamicSiLibraryPpi->PmcClearPowerFailureStatus ();
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}
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///----------------------------------------------------------------------------------
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///
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/// Clear PWR_BTN_STS if set. BIOS should check the WAK_STS bit in PM1_STS[15] (PCH register ABASE+00h) before memory
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/// initialization to determine if ME has reset the system while the Host was in a sleep state.
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/// If WAK_STS is not set, BIOS should ensure a non-sleep exit path is taken by overwriting
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/// PM1_CNT[12:10] (PCH register ABASE+04h) to 111b to force an s5 exit.
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///
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ABase = DynamicSiLibraryPpi->PmcGetAcpiBase ();
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Pm1Sts = IoRead16 (ABase + R_ACPI_IO_PM1_STS);
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if ((Pm1Sts & B_ACPI_IO_PM1_STS_PWRBTN) == B_ACPI_IO_PM1_STS_PWRBTN) {
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IoWrite16 (ABase + R_ACPI_IO_PM1_STS, B_ACPI_IO_PM1_STS_PWRBTN);
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}
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if ((Pm1Sts & B_ACPI_IO_PM1_STS_WAK) == 0) {
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Pm1Cnt = IoRead32 (ABase + R_ACPI_IO_PM1_CNT);
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Pm1Cnt |= V_ACPI_IO_PM1_CNT_S5;
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IoWrite32 (ABase + R_ACPI_IO_PM1_CNT, Pm1Cnt);
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}
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//
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// Update Platform Info
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//
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UpdatePlatformInfo (&SysSetupData,&SocketProcessorCoreSetupData,&SocketIioSetupData);
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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BoardInitAfterMemoryInit (
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VOID
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)
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{
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EFI_STATUS Status;
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EFI_BOOT_MODE BootMode;
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UINT16 Pm1Cnt;
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DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
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Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
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if (EFI_ERROR (Status)) {
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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Status = PeiServicesGetBootMode (&BootMode);
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ASSERT_EFI_ERROR (Status);
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//
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// Check if user wants to turn off in PEI phase
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//
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if (BootMode != BOOT_ON_S3_RESUME) {
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DynamicSiLibraryPpi->CheckPowerOffNow ();
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} else {
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Pm1Cnt = IoRead16 (PCH_ACPI_BASE_ADDRESS + R_ACPI_IO_PM1_CNT);
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Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SLP_TYP;
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IoWrite16 (PCH_ACPI_BASE_ADDRESS + R_ACPI_IO_PM1_CNT, Pm1Cnt);
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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BoardInitBeforeTempRamExit (
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VOID
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)
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{
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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BoardInitAfterTempRamExit (
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VOID
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)
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{
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return EFI_SUCCESS;
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}
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/**
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Initialize POC register by Variable.
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@param *SystemConfiguration - Pointer to SystemConfiguration variables.
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@retval EFI_SUCCESS - Success.
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**/
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EFI_STATUS
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UpdatePlatformInfo (
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IN SYSTEM_CONFIGURATION *SystemConfiguration,
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IN SOCKET_PROCESSORCORE_CONFIGURATION *SocketProcessorCoreConfig,
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IN SOCKET_IIO_CONFIGURATION *SocketIioConfig
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)
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{
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EFI_PLATFORM_INFO *PlatformInfo;
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EFI_HOB_GUID_TYPE *GuidHob;
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//
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// Update the PCIE base and 32/64bit PCI resource support
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//
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GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
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ASSERT (GuidHob != NULL);
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if (GuidHob == NULL) {
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return EFI_NOT_FOUND;
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}
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PlatformInfo = GET_GUID_HOB_DATA(GuidHob);
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PlatformInfo->SysData.SysIoApicEnable = PCH_IOAPIC;
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#if MAX_SOCKET <= 4
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if (SocketIioConfig->DevPresIoApicIio[0]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC00_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[1]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC01_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[2]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC02_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[3]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC03_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[4]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC04_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[5]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC05_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[6]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC06_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[7]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC07_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[8]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC08_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[9]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC09_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[10]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC10_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[11]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC11_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[12]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC12_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[13]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC13_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[14]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC14_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[15]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC15_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[16]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC16_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[17]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC17_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[18]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC18_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[19]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC19_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[20]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC20_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[21]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC21_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[22]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC22_IOAPIC);
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}
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if (SocketIioConfig->DevPresIoApicIio[23]) {
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PlatformInfo->SysData.SysIoApicEnable |= (PC23_IOAPIC);
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}
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#else
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// Enable all 32 IOxAPIC
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PlatformInfo->SysData.SysIoApicEnable = 0xFFFFFFFF;
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#endif
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//
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// Check to make sure TsegSize is in range, if not use default.
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//
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if (SocketProcessorCoreConfig->TsegSize > MAX_PROCESSOR_TSEG) {
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SocketProcessorCoreConfig->TsegSize = MAX_PROCESSOR_TSEG; // if out of range make default 64M
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}
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PlatformInfo->MemData.MemTsegSize = (0x400000 << SocketProcessorCoreConfig->TsegSize);
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PlatformInfo->MemData.MemIedSize = PcdGet32 (PcdCpuIEDRamSize);
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//
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// Minimum SMM range in TSEG should be larger than 3M
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//
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ASSERT (PlatformInfo->MemData.MemTsegSize - PlatformInfo->MemData.MemIedSize >= 0x300000);
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return EFI_SUCCESS;
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}
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