/** @file
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EFI Platform Device Data Definition Header File.
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@copyright
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Copyright 1999 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _EFI_PLAT_DEVICE_DATA_H_
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#define _EFI_PLAT_DEVICE_DATA_H_
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#include <Protocol/PciRootBridgeIo.h>
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#include <Protocol/PciIo.h>
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#include <IndustryStandard/Acpi.h>
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#include <IndustryStandard/Pci.h>
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typedef struct {
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UINT8 Dev; // Device numbers of a chain of bridges starting at PCI Bus, behind which this device is located.
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UINT8 Fun; // Function numbers of a chain of bridges starting at PCI Bus, behind which this device is located.
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} DEVICE_DATA_DEV_PATH;
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typedef struct {
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UINT32 UID; // The Root Bridge ID as appears in the device path for that bridge.
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} DEVICE_DATA_RBRG_PATH;
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typedef struct {
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DEVICE_DATA_RBRG_PATH RootBridgePath; // Path to starting PCI Bus from which the SourceBusPath begins. This is used if there are multiple root bridges. Each such bridge will originate a lowest level PCI bus.
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DEVICE_DATA_DEV_PATH BridgePath[4]; // Pairs of device/function numbers of a chain of bridges starting at PCI Bus, behind which this device is located. Must terminate with Dev = 0xFF. The size of 3 may be bumped up if there is more bus depth levels than 3 on a particular platform.
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} DEVICE_DATA_BUS_PATH;
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//
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// Holds live system PCI Root Bridge info.
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//
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typedef struct {
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EFI_HANDLE Handle; // Handle to the PCI device.
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRbIoProt; // Root Bridge IO protocol.
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EFI_DEVICE_PATH_PROTOCOL *DevPath; // Device path to the bridge.
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Resources; // Bus/IO/Mem ranges exposed via the root bridge.
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} DEVICE_DATA_PCI_RBRG;
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//
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// Holds live system PCI device info.
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//
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typedef struct {
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UINTN Seg;
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UINTN Bus;
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UINTN Dev;
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UINTN Fun;
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} LOCATION;
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typedef struct {
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EFI_HANDLE Handle; // Handle to the PCI device.
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EFI_PCI_IO_PROTOCOL *PciIoProt;
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LOCATION Location; // Bus/Dev/Fun location of this device.
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PCI_TYPE_GENERIC ConfSpace; // First 40h bytes of PCI config space for each device.
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} DEVICE_DATA_PCI_DEV;
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//
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// Holds live system CPU device info.
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//
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typedef struct {
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UINTN PackageNumber;
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UINTN CoreNumber;
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UINTN ThreadNumber;
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UINT8 Present;
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UINT8 Enabled;
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UINT8 Stepping;
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UINT8 Model;
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UINT8 Family;
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UINT8 Bsp;
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UINT8 Apic;
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UINT8 ApicId;
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UINT8 ApicVer;
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UINT8 Fpu;
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UINT8 Mce;
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UINT8 Cx8;
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} DEVICE_DATA_CPU;
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//
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// Platform hardwired data describing all I/O APICs in the system.
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//
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typedef struct {
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UINT8 Enabled;
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UINT32 Address;
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UINT8 Id;
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UINT8 Version;
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} DEVICE_DATA_HW_IO_APIC;
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//
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// Platform hardwired data describing connection of interrupt sources to local APICs.
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//
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typedef struct {
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DEVICE_DATA_BUS_PATH SourceBusPath;
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UINT8 SourceBusIrq;
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UINT8 DestApicId;
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UINT8 DestApicIntIn;
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UINT8 IntType;
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UINT16 Polarity;
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UINT16 Trigger;
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} DEVICE_DATA_HW_LOCAL_INT;
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//
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// Platform hardwired data describing the built-in devices.
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//
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typedef struct {
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DEVICE_DATA_BUS_PATH BusPath; // Path to the device, includes root bridge and P2P bridge chain.
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DEVICE_DATA_DEV_PATH DevFun; // Device/function number of the built-in PCI device being described. 0xff if not applicable e.g., it's an ISA device.
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UINT8 DestApicId; // Destination APIC.
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UINT8 DestApicIntIn; // The pin of the destination APIC the interrupt wire is connected to.
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UINT8 IntType; // As defined in the MPS.
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UINT16 Polarity; // As defined in the MPS.
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UINT16 Trigger; // As defined in the MPS.
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} DEVICE_DATA_HW_BUILT_IN;
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//
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// Platform hardwired data describing the add-in devices.
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// An add-in device is defined here as a pluggable into a PCI slot.
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// Thus there must be as many entries as there are slots in the system.
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// The devices as defined above may have any complexity (wile complying
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// with the PCI spec) including possibly multiple levels of bridges and buses
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// possibly with multiple devices possibly with multiple functions.
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// The routing of the interrupts from such functions is governed by the
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// PCI-to-PCI Bridge Architecture Specification.
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// It short it requires that functions rotate mod 4 the interrupt assignments
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// (A/B/C/D) with PCI devices of single function devices and that the bus depth
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// does not cause such a rotation.
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//
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typedef struct {
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DEVICE_DATA_BUS_PATH BusPath; // Path to the device, includes root bridge and P2P bridge chain.
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UINT8 Dev; // Device number of the slot being described.
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UINT8 DestApicId; // Destination APIC. As defined in the MPS.
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UINT8 DestApicIntIn[4]; // Interrupt pins to destination APIC, indexes correspond to PCI interrupt pins A/B/C/D.
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} DEVICE_DATA_HW_PCI_SLOT;
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//
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// Platform hardwired data describing the address space mapping.
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//
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typedef struct {
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DEVICE_DATA_RBRG_PATH RootBridgePath;
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UINT8 AddressType;
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UINT64 AddressBase;
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UINT64 AddressLength;
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} DEVICE_DATA_HW_ADDR_SPACE_MAPPING;
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//
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// This is the module global containing platform device data.
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//
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typedef struct {
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DEVICE_DATA_HW_LOCAL_INT *LocalIntData;
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UINTN LocalIntDataSize;
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DEVICE_DATA_HW_ADDR_SPACE_MAPPING *AddrDataMapping;
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UINTN AddrDataMappingSize;
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DEVICE_DATA_PCI_RBRG *PciRBridgeInfo; // Info for PCI Root Bridges in the system.
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DEVICE_DATA_PCI_DEV *PciDevInfo; // Info for PCI devices in the system.
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UINT8 PciBusNo; // Number of PCI buses. Assumes that PCI bus numbers are continous and start from 0.
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UINT8 LegacyBusIdx; // Bus number of the legacy bus like ISA. EISA etc. There could only be one legacy bus. It has to be the last bus after all the PCI buses.
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DEVICE_DATA_CPU *CpuInfo; // Info for all processors.
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UINTN CpuMax;
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} DEVICE_DATA;
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//
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// This is the module global containing platform device data.
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//
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typedef struct {
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DEVICE_DATA_HW_PCI_SLOT *HwPciSlotUpdate;
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UINTN HwPciSlotUpdateSize;
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DEVICE_DATA_HW_BUILT_IN *HwBuiltInUpdate;
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UINTN HwBuiltInUpdateSize;
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} DEVICE_UPDATE_DATA;
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typedef struct _MP_TABLE_CPU_INFO {
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UINT8 ApicVersion;
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UINT32 CpuSignature;
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UINT32 FeatureFlags;
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} MP_TABLE_CPU_INFO;
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#endif //_EFI_PLAT_DEVICE_DATA_H_
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