/** @file
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@copyright
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Copyright 2015 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _ONBOARD_NIC_STRUCTS_H
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#define _ONBOARD_NIC_STRUCTS_H
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#include <Protocol/UbaDevsUpdateProtocol.h>
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#pragma pack(1)
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typedef struct {
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NIC_TYPE NicType; //Onboard or IO modue?
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UINT8 NicIndex; //Nic index in setup page, 1 for Nic 1, 2 for Nic 2.....
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//
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//Parent
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//
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UINT8 RootPortBusNo; //Who is connected to?
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UINT8 RootPortDevNo;
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UINT8 RootPortFunNo;
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//
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//Nic controller for Onboard Nic
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//
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UINT16 NicVID; //Vendor ID
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UINT16 NicDID; //Device ID
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UINT8 PortNumbers; //How many ports inside NIC?
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UINT8 DescriptionIndex; //Index to Nic description list
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//
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//Disable Method for Onboard Nic
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//
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UINT8 IsGpioCtrl; //Disable by Gpio?
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UINT32 GpioForDev; //Ctrl Gpio Pin number for device
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UINT8 GpioForDevValue; //what value is used to enable?
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UINT32 PortEnableGPIO[4]; //Ctrl Gpio Pin number for this port
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UINT8 PortEnableGPIOValue[4];//what value is used to enable the port
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UINT8 IsPchNIC;
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} NIC_SETUP_CONFIGURATION_STUCT;
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typedef struct {
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UINT16 NicDID; // Device ID
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UINT16 SubDID; // Subsystem ID, if preset to 0xFFFF, then negore this field during detection
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UINT8 NIC10Gb; // 10Gbe Pxe Seupported
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UINT8 PXE_Support; // Pxe supported?
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UINT8 iSCSI_Support; // iScsi supported?
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UINT8 FCoE_Support; // FCoe supported?
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UINT8 InfB_Support; // InfiniBand supported?
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UINT8 PchNIC; //PCH integrated NIC?
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} NIC_OPTIONROM_CAPBILITY_STRUCT;
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typedef struct {
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UINT16 IOM1DID; //Device ID for IOM1
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UINT16 IOM1SubDID; //Subsystem ID for IOM1
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UINT16 IOM2DID; //Device ID for IOM2
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UINT16 IOM2SubDID; //Subsystem ID for IOM2
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UINT16 IOM3DID; //Device ID for IOM3
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UINT16 IOM3SubDID; //Subsystem ID for IOM3
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UINT16 IOM4DID; //Device ID for IOM4
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UINT16 IOM4SubDID; //Subsystem ID for IOM4
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} IOMS_NV_VARIABLE;
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typedef struct {
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UINT8 PXE10GPreValue;
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UINT8 PXE1GPreValue;
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UINT8 Reserved[6];
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} PXE_PREVIOUS_SETTINGS;
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#pragma pack()
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#define NIC_CHARACTER_NUMBER_FOR_VALUE 30
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#define CPU0_IIO_BUS 0x00
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#define IIO_PCIE_PORT_1A_DEV 0x1
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#define IIO_PCIE_PORT_1A_FUN 0x0
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#define IIO_PCIE_PORT_1B_DEV 0x1
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#define IIO_PCIE_PORT_1B_FUN 0x1
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#define IIO_PCIE_PORT_2A_DEV 0x2
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#define IIO_PCIE_PORT_2A_FUN 0x0
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#define IIO_PCIE_PORT_3A_DEV 0x3
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#define IIO_PCIE_PORT_3A_FUN 0x0
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#define IIO_PCIE_PORT_3C_DEV 0x3
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#define IIO_PCIE_PORT_3C_FUN 0x2
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#define OB_NIC_POWERVILLE_DID 0x1521
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#define INTEL_MAC_ADDRESS_REG 0x5400
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#define VENDOR_ID_MELLANOX 0x15B3
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#define DEVICE_ID_MELLANOX 0x1003
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#endif
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