/** @file
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PCH PCIe Bifurcation Update Library Header File.
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@copyright
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Copyright 2017 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _UBA_PCIE_BIFURCATION_UPDATE_LIB_H
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#define _UBA_PCIE_BIFURCATION_UPDATE_LIB_H
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#include <Base.h>
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#include <Uefi.h>
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#include <Library/PchPcieRpLib.h>
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#define PLATFORM_PCH_PCIE_BIFURCATION_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'P', 'C', 'I')
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#define PLATFORM_PCH_PCIE_BIFURCATION_UPDATE_VERSION 01
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typedef struct {
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UINT8 PortIndex;
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UINT16 SlotNumber; // 0xff if slot not implemented , Slot number if slot implemented
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BOOLEAN InterLockPresent; // Yes / No
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UINT8 SlotPowerLimitScale;
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UINT8 SlotPowerLimitValue;
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BOOLEAN HotPlugCapable; // Yes / No
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UINT8 VppPort; // 0xff if Vpp not enabled
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UINT8 VppAddress;
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BOOLEAN PcieSSDCapable; // Yes / No
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UINT8 PcieSSDVppPort; // 0xff if Vpp not enabled
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UINT8 PcieSSDVppAddress; // 0xff if Vpp not enabled
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BOOLEAN Hidden; // deprecate this as it should be purely based on bifurcation
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BOOLEAN CommonClock; // Yes / No - whether the both side of the link are in same clock domain or not
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BOOLEAN UplinkPortConnected; // Yes / No - indicate the PCIe RP is connected to Uplink port of another chip
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BOOLEAN RetimerConnected; // Yes / No - BIOS would have overhead to bifurcate the retimers explicitly
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UINT8 RetimerSMBusAddress; // SNBus address to read the retimer status and bifurcate if required
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BOOLEAN ExtensionCardSupport; // Yes / No, any PCIe Port extension card which are supported in board thro' SMBus address (typically BW5)
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UINT8 ExtnCardSMBusPort; //SMBus Port for the PCIe extension card - use to dynamically determine PCIe bifurcation
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UINT8 ExtnCardSMBusAddress; //SNBus address for the PCIe extension card - use to dynamically determine PCIe bifurcation
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BOOLEAN ExtnCardRetimerSupport; //yes - retimer on this PCIe extension card (BW5), or No
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UINT8 ExtnCardRetimerSMBusAddress; // SNBus address to read the retimer status and bifurcate if required
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BOOLEAN ExtnCardHotPlugCapable; // yes / No, independent of board, indicates slot in which this PCIe extn. Card is mounted
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UINT8 ExtnCardHPVppPort; // 0xff if VPP not enabled
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UINT8 ExtnCardHPVppAddress; // 0xff if VPP not enabled
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UINT8 RetimerConnectCount; // number of Retimers (1 or 2) intercepted between the PCIe port and the slot device. Retimer may appear mutually exclusive.
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} PCH_SLOT_CONFIG_DATA_ENTRY_EX;
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// {187576ac-fec1-41bf-91f6-7d1ace7f2bee}
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#define PLATFORM_UBA_PCIE_BIFURCATION_GUID \
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{ 0x187576ac, 0xfec1, 0x41bf, { 0x91, 0xf6, 0x7d, 0x1a, 0xce, 0x7f, 0x2b, 0xee } }
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typedef
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EFI_STATUS
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(*PCIE_BIFURCATION_UPDATE_CALLBACK) (
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IN OUT PCIE_BIFURCATION_CONFIG **PchPcieBifurcationConfig,
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IN OUT PCH_SLOT_CONFIG_DATA_ENTRY_EX **PchSlotConfig
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);
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typedef struct _PLATFORM_PCH_PCIE_BIFURCATION_UPDATE_TABLE{
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UINT32 Signature;
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UINT32 Version;
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PCIE_BIFURCATION_UPDATE_CALLBACK CallPcieBifurcationUpdate;
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} PLATFORM_PCH_PCIE_BIFURCATION_UPDATE_TABLE;
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#define ENABLE 1
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#define DISABLE 0
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#define NO_SLT_IMP 0xFF
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#define SLT_IMP 1
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#define HIDE 1
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#define NOT_HIDE 0
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#define VPP_PORT_0 0
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#define VPP_PORT_1 1
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#define VPP_PORT_MAX 0xFF
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#define VPP_ADDR_MAX 0xFF
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#define PWR_VAL_MAX 0xFF
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#define PWR_SCL_MAX 0xFF
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#define SMB_ADDR_MAX 0xFF
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#define NO_BIF_INPUT 0xFF
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#define PORT_0_INDEX 0
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#define PORT_1_INDEX 1
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#define PORT_2_INDEX 2
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#define PORT_3_INDEX 3
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#define PORT_4_INDEX 4
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#define PORT_5_INDEX 5
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#define PORT_6_INDEX 6
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#define PORT_7_INDEX 7
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#define PORT_8_INDEX 8
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#define PORT_9_INDEX 9
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#define PORT_10_INDEX 10
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#define PORT_11_INDEX 11
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#define PORT_12_INDEX 12
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#define PORT_13_INDEX 13
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#define PORT_14_INDEX 14
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#define PORT_15_INDEX 15
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#define PORT_16_INDEX 16 // Added dummy ports(16-27) TODO_FHF
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#define PORT_17_INDEX 17
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#define PORT_18_INDEX 18
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#define PORT_19_INDEX 19
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#define PORT_20_INDEX 20
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#define PORT_21_INDEX 21
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#define PORT_22_INDEX 22
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#define PORT_23_INDEX 23
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#define PORT_24_INDEX 24
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#define PORT_25_INDEX 25
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#define PORT_26_INDEX 26
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#define PORT_27_INDEX 27
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//-----------------------------------------------------------------------------------
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// PCIE port index for SKX
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//------------------------------------------------------------------------------------
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#define SOCKET_0_INDEX 0
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#define SOCKET_1_INDEX 21
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#define SOCKET_2_INDEX 42
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#define SOCKET_3_INDEX 63
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#define SOCKET_4_INDEX 84
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#define SOCKET_5_INDEX 105
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#define SOCKET_6_INDEX 126
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#define SOCKET_7_INDEX 147
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EFI_STATUS
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PlatformGetPchPcieBifurcationConfig (
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IN OUT PCIE_BIFURCATION_CONFIG **PchPcieBifurcationConfig,
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IN OUT PCH_SLOT_CONFIG_DATA_ENTRY_EX **PchSlotConfig
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);
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STATIC EFI_GUID gPlatformUbaPcieBifurcationGuid = PLATFORM_UBA_PCIE_BIFURCATION_GUID;
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#endif //_UBA_PCIE_BIFURCATION_UPDATE_LIB_H
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