/** @file
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UBA IIO Config Library Header File.
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@copyright
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Copyright 2012 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _UBA_IIO_CONFIG_LIB_H
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#define _UBA_IIO_CONFIG_LIB_H
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#include <Base.h>
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#include <Uefi.h>
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#include <IioPlatformData.h>
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#define PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'I', 'I', 'O')
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#define PLATFORM_IIO_CONFIG_UPDATE_VERSION 01
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#define PLATFORM_IIO_CONFIG_UPDATE_VERSION_2 02
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#define PLATFORM_IIO_CONFIG_UPDATE_VERSION_3 03
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#define PLATFORM_IIO_CONFIG_UPDATE_VERSION_UNSUPPORTED 0x20
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// {EB35ED63-EACA-4e29-9516-7EDF1F818837}
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#define PLATFORM_IIO_CONFIG_DATA_GUID \
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{ 0xeb35ed63, 0xeaca, 0x4e29, { 0x95, 0x16, 0x7e, 0xdf, 0x1f, 0x81, 0x88, 0x37 } }
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// {3093F83B-5934-473e-8523-24BF297EE684}
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#define PLATFORM_IIO_CONFIG_DATA_GUID_1 \
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{ 0x3093f83b, 0x5934, 0x473e, { 0x85, 0x23, 0x24, 0xbf, 0x29, 0x7e, 0xe6, 0x84 } }
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// {1C5267A4-634B-4bf2-BFF8-9A1164E6D198}
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#define PLATFORM_IIO_CONFIG_DATA_GUID_2 \
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{ 0x1c5267a4, 0x634b, 0x4bf2, { 0xbf, 0xf8, 0x9a, 0x11, 0x64, 0xe6, 0xd1, 0x98 } }
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// {1E486CCA-048E-4702-B28C-0B677201683A}
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#define PLATFORM_IIO_CONFIG_DATA_GUID_3 \
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{ 0x1e486cca, 0x48e, 0x4702, { 0xb2, 0x8c, 0xb, 0x67, 0x72, 0x1, 0x68, 0x3a } }
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// {6FE6C559-4F35-4111-98E1-332A251512F3}
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#define PLATFORM_IIO_CONFIG_DATA_DXE_GUID \
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{ 0x6fe6c559, 0x4f35, 0x4111, { 0x98, 0xe1, 0x33, 0x2a, 0x25, 0x15, 0x12, 0xf3 } }
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// {0F722F2A-650F-448a-ABB7-04EECD75BB30}
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#define PLATFORM_IIO_CONFIG_DATA_DXE_GUID_1 \
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{ 0xf722f2a, 0x650f, 0x448a, { 0xab, 0xb7, 0x4, 0xee, 0xcd, 0x75, 0xbb, 0x30 } }
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// {EBD11A00-8C5C-4f71-BB9E-5394032B01F4}
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#define PLATFORM_IIO_CONFIG_DATA_DXE_GUID_2 \
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{ 0xebd11a00, 0x8c5c, 0x4f71, { 0xbb, 0x9e, 0x53, 0x94, 0x3, 0x2b, 0x1, 0xf4 } }
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// {123BD082-3201-465c-B139-0CB8C77208F8}
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#define PLATFORM_IIO_CONFIG_DATA_DXE_GUID_3 \
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{ 0x123bd082, 0x3201, 0x465c, { 0xb1, 0x39, 0xc, 0xb8, 0xc7, 0x72, 0x8, 0xf8 } }
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#define ENABLE 1
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#define DISABLE 0
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#define NO_SLT_IMP 0xFF
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#define SLT_IMP 1
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#define HIDE 1
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#define NOT_HIDE 0
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#define VPP_PORT_MAX 0xFF
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#define VPP_ADDR_MAX 0xFF
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#define PWR_VAL_MAX 0xFF
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#define PWR_SCL_MAX 0xFF
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#define SMB_ADDR_MAX 0xFF
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#define SMB_DATA_MAX 0xFF
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#define NO_BIF_INPUT 0xFF
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#define NOT_EXIST 0xFF
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typedef
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EFI_STATUS
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(*IIO_VAR_UPDATE_CALLBACK) (
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IN IIO_GLOBALS *IioGlobalData
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);
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typedef struct _PLATFORM_IIO_BIFURCATION_ENTRY {
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UINT8 Socket;
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UINT8 IouNumber;
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UINT8 Bifurcation;
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} IIO_BIFURCATION_DATA_ENTRY;
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typedef struct _PLATFORM_IIO_BIFURCATION_ENTRY_EX {
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UINT8 Socket;
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UINT8 IouNumber;
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UINT8 Bifurcation;
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UINT8 ExtnCardSMBusPort; //SMBus Port for the PCIe extension card - use to dynamically determine PCIe bifurcation
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UINT8 ExtnCardSMBusAddress; //SMBus address for the PCIe extension card - use to dynamically determine PCIe bifurcation
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UINT8 MuxSMBusAddress; // SMBus address for the Mux - used to communicate to different group of devices
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UINT8 MuxSMBusChannel; // SMBus channel for the Mux - used to select the channel that will be used to communicate to the different group of devices.
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} IIO_BIFURCATION_DATA_ENTRY_EX;
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typedef struct _PLATFORM_IIO_SLOT_ENTRY {
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UINT8 PortIndex;
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UINT16 SlotNumber; // 0xff if slot not implemented , Slot number if slot implemented
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BOOLEAN InterLockPresent;
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UINT8 SlotPowerLimitScale;
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UINT8 SlotPowerLimitValue;
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BOOLEAN HotPlugCapable;
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UINT8 VppPort; // 0xff if Vpp not enabled
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UINT8 VppAddress;
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BOOLEAN PcieSSDCapable;
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UINT8 PcieSSDVppPort; // 0xff if Vpp not enabled
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UINT8 PcieSSDVppAddress;
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BOOLEAN Hidden;
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} IIO_SLOT_CONFIG_DATA_ENTRY;
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typedef struct _PLATFORM_IIO_SLOT_ENTRY_EX {
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UINT8 PortIndex; //( {1,2,3,4} = {1A,,1B,,1C,1D} ), ( {5,6,7,8} = {2A,2B,2C,2D} ), ( {9,10,11,12} = {3A,3B,3C,3D}),...
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UINT16 SlotNumber; // 0xff if slot not implemented , Slot number if slot implemented
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BOOLEAN InterLockPresent; // Yes / No
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UINT8 SlotPowerLimitScale;
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UINT8 SlotPowerLimitValue;
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BOOLEAN HotPlugCapable; // Yes / No
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UINT8 VppPort; // 0xff if Vpp not enabled
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UINT8 VppAddress;
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BOOLEAN PcieSSDCapable; // Yes / No
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UINT8 PcieSSDVppPort; // 0xff if Vpp not enabled
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UINT8 PcieSSDVppAddress; // 0xff if Vpp not enabled
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BOOLEAN Hidden; // deprecate this as it should be purely based on bifurcation
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BOOLEAN CommonClock; // Yes / No - whether the both side of the link are in same clock domain or not
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BOOLEAN SRIS; // Yes / No - in case of distinct clocking whether the separate ref. clk supports SSC or not
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BOOLEAN UplinkPortConnected; // Yes / No - indicate the PCIe RP is connected to Uplink port of another chip
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BOOLEAN RetimerConnected; // Yes / No - BIOS would have overhead to bifurcate the retimers explicitly
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UINT8 RetimerSMBusAddress; // SMBus address to read the retimer status and bifurcate if required
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UINT8 RetimerSMBusChannel; // SMBus Mux channel to read the retimer status and bifurcate if required
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UINT8 RetimerWidth; // Retimer width to determine adjacent Retimers for the same PCIe slot
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UINT8 MuxSMBusAddress; // SMBus address for the Mux - used to communicate to different group of devices
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UINT8 MuxSMBusChannel; // SMBus channel for the Mux - used to select the channel that will be used to communicate to the different group of devices.
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BOOLEAN ExtensionCardSupport; // Yes / No, any PCIe Port extension card which are supported in board thro' SMBus address (typically BW5)
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UINT8 ExtnCardSMBusPort; //SMBus Port for the PCIe extension card - use to dynamically determine PCIe bifurcation
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UINT8 ExtnCardSMBusAddress; //SMBus address for the PCIe extension card - use to dynamically determine PCIe bifurcation
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BOOLEAN ExtnCardRetimerSupport; //yes - retimer on this PCIe extension card (BW5), or No
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UINT8 ExtnCardRetimerSMBusAddress; // SMBus address to read the retimer status and bifurcate if required
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UINT8 ExtnCardRetimerWidth; // use to determine adjacent Retimers to the x16 PCIe slot on which this Riser is mounted
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BOOLEAN ExtnCardHotPlugCapable; // yes / No, independent of board, indicates slot in which this PCIe extn. Card is mounted
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UINT8 ExtnCardHPVppPort; // 0xff if VPP not enabled
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UINT8 ExtnCardHPVppAddress; // 0xff if VPP not enabled
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UINT8 RetimerConnectCount; // number of Retimers (1 or 2) intercepted between the PCIe port and the slot device. Retimer may appear mutually exclusive.
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} IIO_SLOT_CONFIG_DATA_ENTRY_EX;
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typedef struct _PLATFORM_IIO_CONFIG_UPDATE_TABLE {
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UINT32 Signature;
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UINT32 Version;
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IIO_BIFURCATION_DATA_ENTRY *IioBifurcationTablePtr;
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UINTN IioBifurcationTableSize;
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IIO_VAR_UPDATE_CALLBACK CallUpdate;
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IIO_SLOT_CONFIG_DATA_ENTRY *IioSlotTablePtr;
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UINTN IioSlotTableSize;
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} PLATFORM_IIO_CONFIG_UPDATE_TABLE;
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typedef struct _PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX {
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UINT32 Signature;
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UINT32 Version;
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IIO_BIFURCATION_DATA_ENTRY_EX *IioBifurcationTablePtr;
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UINTN IioBifurcationTableSize;
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IIO_VAR_UPDATE_CALLBACK CallUpdate;
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IIO_SLOT_CONFIG_DATA_ENTRY_EX *IioSlotTablePtr;
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UINTN IioSlotTableSize;
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} PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX;
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typedef struct {
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UINT8 MuxSmbAddress;
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UINT8 MuxSmbChannel;
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UINT8 SmbAddress0;
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UINT8 SmbAddress1;
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UINT8 RegOffset;
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UINT8 RegValue;
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} MUX_SMB_ADDR;
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typedef struct _PLATFORM_IIO_CONFIG_UPDATE_TABLE_3 {
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UINT32 Signature;
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UINT32 Version;
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IIO_BIFURCATION_DATA_ENTRY_EX *IioBifurcationTablePtr;
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UINTN IioBifurcationTableSize;
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IIO_VAR_UPDATE_CALLBACK CallUpdate;
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IIO_SLOT_CONFIG_DATA_ENTRY_EX *IioSlotTablePtr;
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UINTN IioSlotTableSize;
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MUX_SMB_ADDR *RetimerInitTablePtr;
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} PLATFORM_IIO_CONFIG_UPDATE_TABLE_3;
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typedef struct {
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UINT8 PortHide[8];
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} PCIE_PORT_HIDE_TABLE;
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EFI_STATUS
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PlatformIioConfigInit (
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IN OUT IIO_BIFURCATION_DATA_ENTRY **BifurcationTable,
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IN OUT UINT8 *BifurcationEntries,
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IN OUT IIO_SLOT_CONFIG_DATA_ENTRY **SlotTable,
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IN OUT UINT8 *SlotEntries
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);
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EFI_STATUS
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PlatformIioConfigInit2 (
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IN UINT8 SkuPersonalityType,
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IN OUT IIO_BIFURCATION_DATA_ENTRY **BifurcationTable,
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IN OUT UINT8 *BifurcationEntries,
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IN OUT IIO_SLOT_CONFIG_DATA_ENTRY **SlotTable,
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IN OUT UINT8 *SlotEntries
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);
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EFI_STATUS
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PlatformUpdateIioConfig (
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IN IIO_GLOBALS *IioGlobalData
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);
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EFI_STATUS
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PlatformUpdateIioConfig_EX (
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IN IIO_GLOBALS *IioGlobalData
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);
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STATIC EFI_GUID gPlatformIioConfigDataGuid = PLATFORM_IIO_CONFIG_DATA_GUID;
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STATIC EFI_GUID gPlatformIioConfigDataGuid_1 = PLATFORM_IIO_CONFIG_DATA_GUID_1;
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STATIC EFI_GUID gPlatformIioConfigDataGuid_2 = PLATFORM_IIO_CONFIG_DATA_GUID_2;
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STATIC EFI_GUID gPlatformIioConfigDataGuid_3 = PLATFORM_IIO_CONFIG_DATA_GUID_3;
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STATIC EFI_GUID gPlatformIioConfigDataDxeGuid = PLATFORM_IIO_CONFIG_DATA_DXE_GUID;
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STATIC EFI_GUID gPlatformIioConfigDataDxeGuid_1 = PLATFORM_IIO_CONFIG_DATA_DXE_GUID_1;
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STATIC EFI_GUID gPlatformIioConfigDataDxeGuid_2 = PLATFORM_IIO_CONFIG_DATA_DXE_GUID_2;
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STATIC EFI_GUID gPlatformIioConfigDataDxeGuid_3 = PLATFORM_IIO_CONFIG_DATA_DXE_GUID_3;
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#endif //_UBA_IIO_CONFIG_LIB_H
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