## @file
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# PCD configuration build description file for the UpXtreme board.
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#
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# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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################################################################################
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#
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# Pcd Section - list of all PCD Entries used by this board.
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#
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################################################################################
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[PcdsFixedAtBuild.common]
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######################################
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# Key Boot Stage and FSP configuration
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######################################
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#
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# Please select the Boot Stage here.
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# Stage 1 - enable debug (system deadloop after debug init)
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# Stage 2 - mem init (system deadloop after mem init)
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# Stage 3 - boot to shell only
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# Stage 4 - boot to OS
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# Stage 5 - boot to OS with security boot enabled
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# Stage 6 - boot with advanced features enabled
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#
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gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
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#
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# 0: FSP Wrapper is running in Dispatch mode.
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# 1: FSP Wrapper is running in API mode.
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# Note: Dispatch mode is currently NOT supported for this board.
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#
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1
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#
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# FALSE: The board is not a FSP wrapper (FSP binary not used)
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# TRUE: The board is a FSP wrapper (FSP binary is used)
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#
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gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
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#
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# FSP Base address PCD will be updated in FDF basing on flash map.
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#
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gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
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gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
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gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
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gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
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gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
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gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
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#
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# When sharing stack with boot loader, FSP only needs a small temp ram for heap
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#
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gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x10000
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#
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# Boot loader stack size has to be large enough for FSP execution
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#
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gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x30000
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gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
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gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
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[PcdsFeatureFlag.common]
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######################################
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# Edk2 Configuration
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######################################
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gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
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gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
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######################################
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# Silicon Configuration
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######################################
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# Build switches
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gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
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# CPU
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gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
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# SA
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gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE
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# ME
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gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
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gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE
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# Others
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gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE
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gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
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gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE
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gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE - HPET / FALSE - 8254 timer is used.
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######################################
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# Platform Configuration
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######################################
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gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|TRUE
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
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gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
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gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
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gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
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!endif
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!if $(TARGET) == DEBUG
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gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
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!else
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gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
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!endif
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######################################
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# Board Configuration
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######################################
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable|TRUE
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE
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[PcdsFixedAtBuild.common]
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######################################
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# Edk2 Configuration
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######################################
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!if $(TARGET) == RELEASE
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gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
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gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
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!else
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gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
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gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
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gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
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!endif
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gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
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gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
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gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
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gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
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gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
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!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
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gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
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!endif
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gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000
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gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE
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!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
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gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
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!endif
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gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
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#
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# Serial UART settings
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#
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|115200
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|1843200
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0x19, 0x02, 0x84, 0x00, 0xFF}
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterAccessWidth|8
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xFE036000
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE
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gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
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!if $(TARGET) == RELEASE
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gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
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!else
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gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
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!endif
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
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# Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
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#
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# In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild
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# (They will be DynamicEx in FSP Dispatch mode)
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#
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## Specifies the size of the microcode Region.
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# @Prompt Microcode Region size.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0
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## Specifies the AP wait loop state during POST phase.
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# The value is defined as below.
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# 1: Place AP in the Hlt-Loop state.
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# 2: Place AP in the Mwait-Loop state.
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# 3: Place AP in the Run-Loop state.
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# @Prompt The AP wait loop state.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
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######################################
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# Silicon Configuration
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######################################
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!if $(TARGET) == DEBUG
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gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
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!endif
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gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2
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gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
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######################################
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# Platform Configuration
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######################################
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gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1
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gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
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gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
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#
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# The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
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#
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# BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions.
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# BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \
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# that lie entirely within the expected fixed memory regions.
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# BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms.
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# BIT3-31: Reserved
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#
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gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
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!if $(TARGET) == RELEASE
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402
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!else
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B
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!endif
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b
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!if $(TARGET) == RELEASE
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70
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!else
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 1
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gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 2
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gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 3
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gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 4
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gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 5
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gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6
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gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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!endif
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######################################
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# Board Configuration
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######################################
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gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable|0
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gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x00, 0x00, 0x1F, 0x00}
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[PcdsFixedAtBuild.IA32]
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######################################
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# Edk2 Configuration
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######################################
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gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
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gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
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gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
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######################################
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# Platform Configuration
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######################################
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gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000
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[PcdsFixedAtBuild.X64]
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######################################
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# Edk2 Configuration
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######################################
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# Default platform supported RFC 4646 languages: (American) English
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gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US"
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[PcdsPatchableInModule.common]
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######################################
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# Edk2 Configuration
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######################################
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gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208
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gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
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[PcdsDynamicDefault]
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######################################
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# Edk2 Configuration
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######################################
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gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE
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gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE
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gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
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#
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# Set video to native resolution as Windows 8 WHCK requirement.
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#
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gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0
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gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00
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#
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# FSP Base address PCD will be updated in FDF basing on flash map.
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#
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
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# Platform will pre-allocate UPD buffer and pass it to FspWrapper
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# Those dummy address will be patched before FspWrapper executing
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
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######################################
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# Board Configuration
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######################################
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# Thunderbolt Configuration
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm|0x0
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel|0x1
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify|0x1
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI|0x1
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd|100
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0x1
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport|0x0
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt|0x1
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq|0x1
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gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDciEnable|FALSE
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[PcdsDynamicHii.X64.DEFAULT]
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######################################
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# Edk2 Configuration
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######################################
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gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
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!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
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gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout"
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!else
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gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
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!endif
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