/** @file
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiPei.h>
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#include <SaPolicyCommon.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/IoLib.h>
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#include <Library/HobLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/PciLib.h>
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#include <Library/PcdLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/PeiSaPolicyLib.h>
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#include <Library/BoardInitLib.h>
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#include <PchAccess.h>
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#include <Library/GpioNativeLib.h>
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#include <Library/GpioLib.h>
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#include <GpioPinsSklLp.h>
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#include <GpioPinsSklH.h>
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#include <Library/GpioExpanderLib.h>
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#include <SioRegs.h>
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#include <Library/PchPcrLib.h>
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#include "UpXtremeInit.h"
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#include <ConfigBlock.h>
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#include <Setup.h>
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#include <ConfigBlock/MemoryConfig.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchInfoLib.h>
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#include <Register/PchRegsPcr.h>
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#include <Library/PchResetLib.h>
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#include <Register/PchRegsLpc.h>
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#include <Library/StallPpiLib.h>
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#include <Library/PeiPolicyInitLib.h>
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#include <Ppi/Reset.h>
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#include <PlatformBoardConfig.h>
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#include <GpioPinsCnlLp.h>
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#include <Library/PmcLib.h>
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#include <Library/PciSegmentLib.h>
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#include <PeiPlatformHookLib.h>
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#include <FirwmareConfigurations.h>
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#include <Guid/TcoWdtHob.h>
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#include <Library/OcWdtLib.h>
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#include <CpuRegs.h>
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#include <Library/BaseLib.h>
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///
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/// Reset Generator I/O Port
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///
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#define RESET_GENERATOR_PORT 0xCF9
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typedef struct {
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EFI_PHYSICAL_ADDRESS BaseAddress;
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UINT64 Length;
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} MEMORY_MAP;
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GLOBAL_REMOVE_IF_UNREFERENCED MEMORY_MAP MmioMap[] = {
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{ FixedPcdGet64(PcdApicLocalAddress), FixedPcdGet32(PcdApicLocalMmioSize) },
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{ FixedPcdGet64(PcdMchBaseAddress), FixedPcdGet32(PcdMchMmioSize) },
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{ FixedPcdGet64(PcdDmiBaseAddress), FixedPcdGet32(PcdDmiMmioSize) },
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{ FixedPcdGet64(PcdEpBaseAddress), FixedPcdGet32(PcdEpMmioSize) },
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{ FixedPcdGet64(PcdGdxcBaseAddress), FixedPcdGet32(PcdGdxcMmioSize) }
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};
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EFI_STATUS
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MrcConfigInit(
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IN UINT16 BoardId
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);
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EFI_STATUS
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SaGpioConfigInit(
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IN UINT16 BoardId
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);
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EFI_STATUS
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SaMiscConfigInit(
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IN UINT16 BoardId
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);
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EFI_STATUS
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RootPortClkInfoInit(
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IN UINT16 BoardId
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);
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EFI_STATUS
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UsbConfigInit(
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IN UINT16 BoardId
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);
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EFI_STATUS
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GpioGroupTierInit(
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IN UINT16 BoardId
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);
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EFI_STATUS
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GpioTablePreMemInit(
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IN UINT16 BoardId
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);
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EFI_STATUS
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PchPmConfigInit(
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IN UINT16 BoardId
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);
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EFI_STATUS
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SaDisplayConfigInit(
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IN UINT16 BoardId
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);
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EFI_STATUS
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EFIAPI
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PlatformInitPreMemCallBack(
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
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IN VOID *Ppi
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);
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EFI_STATUS
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EFIAPI
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MemoryDiscoveredPpiNotify(
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
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IN VOID *Ppi
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);
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EFI_STATUS
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EFIAPI
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PchReset(
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IN CONST EFI_PEI_SERVICES **PeiServices
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);
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static EFI_PEI_RESET_PPI mResetPpi = {
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PchReset
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};
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static EFI_PEI_PPI_DESCRIPTOR mPreMemPpiList[] = {
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{
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(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEfiPeiResetPpiGuid,
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&mResetPpi
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}
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};
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static EFI_PEI_NOTIFY_DESCRIPTOR mPreMemNotifyList = {
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(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEfiPeiReadOnlyVariable2PpiGuid,
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(EFI_PEIM_NOTIFY_ENTRY_POINT)PlatformInitPreMemCallBack
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};
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static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
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(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEfiPeiMemoryDiscoveredPpiGuid,
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(EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotify
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};
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/**
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Board misc init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integer represent the board id.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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BoardMiscInitPreMem(
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IN UINT16 BoardId
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)
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{
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//
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// Configure WWAN Full Card Power Off and reset pins
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//
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switch (BoardId) {
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// todo for UP Xtreme
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case BoardIdWhiskeyLakeRvp:
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//
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// According to board default settings, GPP_D16 is used to enable/disable modem
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// power. An alternative way to contol modem power is to toggle FCP_OFF via GPP_D13
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// but board rework is required.
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//
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PcdSet32S (PcdWwanFullCardPowerOffGpio, GPIO_CNL_LP_GPP_D16);
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PcdSet32S (PcdWwanBbrstGpio, GPIO_CNL_LP_GPP_F1);
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PcdSet32S (PcdWwanPerstGpio, GPIO_CNL_LP_GPP_E15);
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PcdSet8S (PcdWwanPerstGpioPolarity, 1);
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break;
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default:
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break;
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}
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//
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// Pc8374SioKbc Present
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//
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PcdSetBoolS (PcdPc8374SioKbcPresent, FALSE);
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return EFI_SUCCESS;
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}
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//@todo it should be moved to Si Pkg.
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/**
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Early Platform PCH initialization
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**/
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VOID
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EarlyPlatformPchInit(
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VOID
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)
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{
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UINT8 Data8;
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UINT16 Data16;
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UINT8 TcoRebootHappened;
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TCO_WDT_HOB *TcoWdtHobPtr;
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EFI_STATUS Status;
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///
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/// Halt the TCO timer
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///
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Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT);
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Data16 |= B_TCO_IO_TCO1_CNT_TMR_HLT;
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IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT, Data16);
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///
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/// Read the Second TO status bit
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///
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Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS);
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if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) == B_TCO_IO_TCO2_STS_SECOND_TO) {
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TcoRebootHappened = 1;
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DEBUG ((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit is set. This might be a TCO reboot\n"));
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}
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else {
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TcoRebootHappened = 0;
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}
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///
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/// Create HOB
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///
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Status = PeiServicesCreateHob (EFI_HOB_TYPE_GUID_EXTENSION, sizeof (TCO_WDT_HOB), (VOID **) &TcoWdtHobPtr);
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if (!EFI_ERROR (Status)) {
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TcoWdtHobPtr->Header.Name = gTcoWdtHobGuid;
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TcoWdtHobPtr->TcoRebootHappened = TcoRebootHappened;
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}
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///
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/// Clear the Second TO status bit
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///
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IoWrite8 (PcdGet16(PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS, B_TCO_IO_TCO2_STS_SECOND_TO);
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}
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/**
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Board configuration initialization in the pre-memory boot phase.
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**/
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VOID
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BoardConfigInitPreMem (
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VOID
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)
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{
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EFI_STATUS Status;
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UINT16 BoardId;
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BoardId = BoardIdUpXtreme;
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Status = MrcConfigInit (BoardId);
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ASSERT_EFI_ERROR (Status);
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Status = SaGpioConfigInit (BoardId);
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ASSERT_EFI_ERROR (Status);
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Status = SaMiscConfigInit (BoardId);
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ASSERT_EFI_ERROR (Status);
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Status = RootPortClkInfoInit (BoardId);
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ASSERT_EFI_ERROR (Status);
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Status = UsbConfigInit (BoardId);
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ASSERT_EFI_ERROR (Status);
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Status = GpioGroupTierInit (BoardId);
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ASSERT_EFI_ERROR (Status);
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Status = GpioTablePreMemInit (BoardId);
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ASSERT_EFI_ERROR (Status);
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Status = PchPmConfigInit (BoardId);
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ASSERT_EFI_ERROR (Status);
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Status = BoardMiscInitPreMem (BoardId);
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ASSERT_EFI_ERROR (Status);
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Status = SaDisplayConfigInit (BoardId);
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ASSERT_EFI_ERROR (Status);
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}
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/**
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This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced
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@param[in] PeiServices Pointer to PEI Services Table.
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@param[in] NotifyDesc Pointer to the descriptor for the Notification event that
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caused this function to execute.
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@param[in] Ppi Pointer to the PPI data associated with this function.
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@retval EFI_SUCCESS The function completes successfully
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@retval others
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**/
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EFI_STATUS
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EFIAPI
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PlatformInitPreMemCallBack(
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
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IN VOID *Ppi
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)
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{
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EFI_STATUS Status;
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UINT16 ABase;
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UINT8 FwConfig;
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//
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// Init Board Config Pcd.
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//
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BoardConfigInitPreMem ();
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FwConfig = FwConfigProduction;
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PcdSetBoolS (PcdPcieWwanEnable, FALSE);
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PcdSetBoolS (PcdWwanResetWorkaround, FALSE);
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//
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// Early Board Configuration before memory is ready.
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//
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Status = BoardInitEarlyPreMem ();
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ASSERT_EFI_ERROR (Status);
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///
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/// If there was unexpected reset but no WDT expiration and no resume from S3/S4,
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/// clear unexpected reset status and enforce expiration. This is to inform Firmware
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/// which has no access to unexpected reset status bit, that something went wrong.
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///
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OcWdtResetCheck ();
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Status = OcWdtInit ();
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ASSERT_EFI_ERROR (Status);
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//
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// Initialize Intel PEI Platform Policy
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//
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PeiPolicyInitPreMem (FwConfig);
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///
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/// Configure GPIO and SIO
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///
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Status = BoardInitPreMem ();
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ASSERT_EFI_ERROR (Status);
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ABase = PmcGetAcpiBase ();
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///
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/// Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI.
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///
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IoWrite16 (ABase + R_ACPI_IO_PM1_EN, 0);
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IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0);
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///
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/// Install Pre Memory PPIs
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///
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Status = PeiServicesInstallPpi (&mPreMemPpiList[0]);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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/**
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Provide hard reset PPI service.
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To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xCF9).
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@param[in] PeiServices General purpose services available to every PEIM.
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@retval Not return System reset occured.
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@retval EFI_DEVICE_ERROR Device error, could not reset the system.
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**/
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EFI_STATUS
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EFIAPI
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PchReset(
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IN CONST EFI_PEI_SERVICES **PeiServices
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)
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{
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DEBUG ((DEBUG_INFO, "Perform Cold Reset\n"));
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IoWrite8 (RESET_GENERATOR_PORT, 0x0E);
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CpuDeadLoop ();
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///
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/// System reset occured, should never reach at this line.
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///
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ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
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return EFI_DEVICE_ERROR;
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}
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/**
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Install Firmware Volume Hob's once there is main memory
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@param[in] PeiServices General purpose services available to every PEIM.
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@param[in] NotifyDescriptor Notify that this module published.
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@param[in] Ppi PPI that was installed.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
|
EFIAPI
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MemoryDiscoveredPpiNotify(
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
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IN VOID *Ppi
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)
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{
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EFI_STATUS Status;
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EFI_BOOT_MODE BootMode;
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UINTN Index;
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UINT8 PhysicalAddressBits;
|
UINT32 RegEax;
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MEMORY_MAP PcieMmioMap;
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Index = 0;
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Status = PeiServicesGetBootMode (&BootMode);
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ASSERT_EFI_ERROR (Status);
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000008) {
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AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
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PhysicalAddressBits = (UINT8) RegEax;
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}
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else {
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PhysicalAddressBits = 36;
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}
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///
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/// Create a CPU hand-off information
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///
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BuildCpuHob (PhysicalAddressBits, 16);
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///
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/// Build Memory Mapped IO Resource which is used to build E820 Table in LegacyBios.
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///
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PcieMmioMap.BaseAddress = FixedPcdGet64 (PcdPciExpressBaseAddress);
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PcieMmioMap.Length = PcdGet32 (PcdPciExpressRegionLength);
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BuildResourceDescriptorHob (
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EFI_RESOURCE_MEMORY_MAPPED_IO,
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(EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
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PcieMmioMap.BaseAddress,
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PcieMmioMap.Length
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);
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BuildMemoryAllocationHob (
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PcieMmioMap.BaseAddress,
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PcieMmioMap.Length,
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EfiMemoryMappedIO
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);
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for (Index = 0; Index < sizeof (MmioMap) / (sizeof (MEMORY_MAP)); Index++) {
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BuildResourceDescriptorHob (
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EFI_RESOURCE_MEMORY_MAPPED_IO,
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(EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
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MmioMap[Index].BaseAddress,
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MmioMap[Index].Length
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);
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BuildMemoryAllocationHob (
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MmioMap[Index].BaseAddress,
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MmioMap[Index].Length,
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EfiMemoryMappedIO
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);
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}
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//
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// Report resource HOB for flash FV
|
//
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BuildResourceDescriptorHob (
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EFI_RESOURCE_MEMORY_MAPPED_IO,
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(EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
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(UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
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(UINTN) FixedPcdGet32 (PcdFlashAreaSize)
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);
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BuildMemoryAllocationHob (
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(UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
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(UINTN) FixedPcdGet32 (PcdFlashAreaSize),
|
EfiMemoryMappedIO
|
);
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BuildFvHob (
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(UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
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(UINTN) FixedPcdGet32 (PcdFlashAreaSize)
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);
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return Status;
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}
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|
|
/**
|
Board configuration init function for PEI pre-memory phase.
|
|
@retval EFI_SUCCESS The function completed successfully.
|
@retval EFI_INVALID_PARAMETER The parameter is NULL.
|
**/
|
EFI_STATUS
|
EFIAPI
|
UpXtremeInitPreMem (
|
VOID
|
)
|
{
|
EFI_STATUS Status;
|
|
///
|
/// Install Stall PPI
|
///
|
Status = InstallStallPpi ();
|
ASSERT_EFI_ERROR (Status);
|
|
///@todo it should be moved to Si Pkg.
|
///
|
/// Do Early PCH init
|
///
|
EarlyPlatformPchInit ();
|
|
//
|
// Install PCH RESET PPI and EFI RESET2 PeiService
|
//
|
Status = PchInitializeReset ();
|
ASSERT_EFI_ERROR (Status);
|
|
///
|
/// Performing PlatformInitPreMemCallBack after PeiReadOnlyVariable2 PPI produced
|
///
|
Status = PeiServicesNotifyPpi (&mPreMemNotifyList);
|
|
///
|
/// After code reorangized, memorycallback will run because the PPI is already
|
/// installed when code run to here, it is supposed that the InstallEfiMemory is
|
/// done before.
|
///
|
Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
|
|
return EFI_SUCCESS;
|
}
|
|
/**
|
Configure GPIO and SIO before memory ready
|
|
@retval EFI_SUCCESS Operation success.
|
**/
|
EFI_STATUS
|
EFIAPI
|
UpXtremeBoardInitBeforeMemoryInit (
|
VOID
|
)
|
{
|
UpXtremeInitPreMem ();
|
|
return EFI_SUCCESS;
|
}
|
|
EFI_STATUS
|
EFIAPI
|
UpXtremeBoardDebugInit (
|
VOID
|
)
|
{
|
// Serial port initialization is performed in the PlatformHookSerialPortInitialize ()
|
// function invoked by SerialPortInitialize () in SerialPortLib
|
DEBUG_CODE_BEGIN();
|
DEBUG_CONFIG_DATA_HOB *DebugConfigDataHob;
|
|
DebugConfigDataHob = BuildGuidHob (&gDebugConfigHobGuid, sizeof (DEBUG_CONFIG_DATA_HOB));
|
ASSERT (DebugConfigDataHob != NULL);
|
if (DebugConfigDataHob == NULL) {
|
DEBUG ((DEBUG_ERROR, "Build Debug Config Hob failed!\n"));
|
return EFI_OUT_OF_RESOURCES;
|
}
|
|
switch (PcdGet32 (PcdSerialBaudRate)) {
|
case 9600:
|
DebugConfigDataHob->SerialDebugBaudRate = 3;
|
break;
|
case 19200:
|
DebugConfigDataHob->SerialDebugBaudRate = 4;
|
break;
|
case 57600:
|
DebugConfigDataHob->SerialDebugBaudRate = 6;
|
break;
|
default:
|
DebugConfigDataHob->SerialDebugBaudRate = 7;
|
}
|
DebugConfigDataHob->SerialDebug = 0x3;
|
DebugConfigDataHob->RamDebugInterface = 0;
|
DebugConfigDataHob->UartDebugInterface = 0;
|
DebugConfigDataHob->Usb3DebugInterface = 0;
|
DebugConfigDataHob->SerialIoDebugInterface = (FeaturePcdGet (PcdSerialIoUartEnable)) ? 1 : 0;
|
DebugConfigDataHob->TraceHubDebugInterface = 0;
|
|
DEBUG_CODE_END();
|
|
return EFI_SUCCESS;
|
}
|
|
EFI_BOOT_MODE
|
EFIAPI
|
UpXtremeBoardBootModeDetect (
|
VOID
|
)
|
{
|
return BOOT_WITH_FULL_CONFIGURATION;
|
}
|
|
|
