/** @file
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Source code for the board SA configuration Pcd init functions in Pre-Memory init phase.
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "BoardSaConfigPreMem.h"
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#include "SaPolicyCommon.h"
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#include "UpXtremeInit.h"
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#include <PlatformBoardConfig.h>
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#include <Library/CpuPlatformLib.h>
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//
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// Display DDI settings for UP Xtreme
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//
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GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mUpXtremeRowDisplayDdiConfig[9] = {
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DdiPortAEdp, // DDI Port A Config : DdiPortADisabled = Disabled, DdiPortAEdp = eDP, DdiPortAMipiDsi = MIPI DSI
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DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
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DdiHpdEnable, // DDI Port C HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
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DdiHpdEnable, // DDI Port D HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
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DdiHpdEnable, // DDI Port F HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
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DdiDdcEnable, // DDI Port B DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
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DdiDdcEnable, // DDI Port C DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
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DdiDdcEnable, // DDI Port D DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
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DdiDisable // DDI Port F DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
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};
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/**
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MRC configuration init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integer represent the board id.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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SaMiscConfigInit (
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IN UINT16 BoardId
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)
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{
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//
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// UserBd
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//
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switch (BoardId) {
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case BoardIdUpXtreme:
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//
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// Assign UserBd to 5 which is assigned to MrcInputs->BoardType btUser4 for ULT platforms.
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// This is required to skip Memory voltage programming based on GPIO's in MRC
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//
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PcdSet8S (PcdSaMiscUserBd, 5); // MrcBoardType btUser4 for UP Xtreme (ULT/ULX/Modile Halo)
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break;
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default:
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// MiscPeiPreMemConfig.UserBd = 0 by default.
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break;
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}
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PcdSet16S (PcdSaDdrFreqLimit, 0);
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return EFI_SUCCESS;
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}
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/**
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Board Memory Init related configuration init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integrer represent the board id.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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MrcConfigInit (
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IN UINT16 BoardId
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)
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{
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CPU_FAMILY CpuFamilyId;
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UINT8 BomId;
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CpuFamilyId = GetCpuFamily();
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if (CpuFamilyId == EnumCpuCflDtHalo) {
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PcdSetBoolS (PcdDualDimmPerChannelBoardType, TRUE);
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} else {
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PcdSetBoolS (PcdDualDimmPerChannelBoardType, FALSE);
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}
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//
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// Example policy for DIMM slots implementation boards:
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// 1. Assign Smbus address of DIMMs and SpdData will be updated later
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// by reading from DIMM SPD.
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// 2. No need to apply hardcoded SpdData buffers here for such board.
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//
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// Whiskey Lake U RVP has removable DIMM slots.
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// So assign all Smbus address of DIMMs and leave PcdMrcSpdData set to 0.
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// Example:
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// PcdMrcSpdData = 0
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// PcdMrcSpdDataSize = 0
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// PcdMrcSpdAddressTable0 = 0xA0
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// PcdMrcSpdAddressTable1 = 0xA2
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// PcdMrcSpdAddressTable2 = 0xA4
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// PcdMrcSpdAddressTable3 = 0xA6
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//
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// If a board has soldered down memory. It should use the following settings.
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// Example:
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// PcdMrcSpdAddressTable0 = 0
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// PcdMrcSpdAddressTable1 = 0
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// PcdMrcSpdAddressTable2 = 0
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// PcdMrcSpdAddressTable3 = 0
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// PcdMrcSpdData = static data buffer
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// PcdMrcSpdDataSize = sizeof (static data buffer)
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//
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//
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// SPD Address Table
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//
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// BOMID [1:0]
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// 0: 16G A & B CH
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// 1: 8G A CH
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// 2: 8G A & B CH
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// 3: 4G A CH
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BomId = PcdGet8(PcdBoardBomId);
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DEBUG ((DEBUG_INFO, "Up Xtreme Bom ID 0x%x\n",BomId));
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if ((BomId & BIT1) == BIT1) {
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PcdSet32S (PcdMrcSpdData, (UINTN) mUpXtremeSamsungDdr4Spd);
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PcdSet16S (PcdMrcSpdDataSize, mUpXtremeSamsungDdr4SpdSize);
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DEBUG ((DEBUG_INFO, "Using Xtreme SPD Samsung Ddr4\n"));
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} else {
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PcdSet32S (PcdMrcSpdData, (UINTN) mUpXtremeSkhynixDdr4Spd);
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PcdSet16S (PcdMrcSpdDataSize, mUpXtremeSkhynixDdr4SpdSize);
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DEBUG ((DEBUG_INFO, "Using Xtreme SPD Skhynix Ddr4\n"));
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}
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PcdSet8S (PcdMrcSpdAddressTable0, 0);
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PcdSet8S (PcdMrcSpdAddressTable1, 0);
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PcdSet8S (PcdMrcSpdAddressTable2, 0);
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PcdSet8S (PcdMrcSpdAddressTable3, 0);
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//
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// DRAM SPD Data & related configuration
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//
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PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapUpXtreme);
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PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapUpXtreme));
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PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramUpXtreme);
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PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramUpXtreme));
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switch (BoardId) {
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case BoardIdUpXtreme:
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PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorUpXtreme);
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PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetUpXtreme);
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PcdSetBoolS (PcdMrcDqPinsInterleavedControl, FALSE);
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PcdSetBoolS (PcdMrcDqPinsInterleaved, FALSE);
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break;
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default:
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break;
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}
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//
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// CA Vref routing: board-dependent
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// 0 - VREF_CA goes to both CH_A and CH_B (LPDDR3/DDR3L)
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// 1 - VREF_CA to CH_A, VREF_DQ_A to CH_B (should not be used)
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// 2 - VREF_CA to CH_A, VREF_DQ_B to CH_B (DDR4)
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//
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switch (BoardId) {
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case BoardIdUpXtreme:
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PcdSet8S (PcdMrcCaVrefConfig, 2); // DDR4 boards
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break;
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default:
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PcdSet8S (PcdMrcCaVrefConfig, 0); // All DDR3L/LPDDR3/LPDDR4 boards
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break;
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}
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return EFI_SUCCESS;
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}
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/**
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Board SA related GPIO configuration init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integer represent the board id.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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SaGpioConfigInit (
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IN UINT16 BoardId
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)
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{
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//
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// Update board's GPIO for PEG slot reset
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//
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PcdSetBoolS (PcdPegGpioResetControl, TRUE);
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PcdSetBoolS (PcdPegGpioResetSupoort, FALSE);
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PcdSet32S (PcdPeg0ResetGpioPad, 0);
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PcdSetBoolS (PcdPeg0ResetGpioActive, FALSE);
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PcdSet32S (PcdPeg3ResetGpioPad, 0);
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PcdSetBoolS (PcdPeg3ResetGpioActive, FALSE);
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//
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// PCIE RTD3 GPIO
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//
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switch (BoardId) {
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// todo for UP Xtreme
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case BoardIdWhiskeyLakeRvp:
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PcdSet8S(PcdRootPortIndex, 4);
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PcdSet8S (PcdPcie0GpioSupport, PchGpio);
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PcdSet32S (PcdPcie0WakeGpioNo, 0);
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PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
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PcdSet32S (PcdPcie0HoldRstGpioNo, GPIO_CNL_LP_GPP_C15);
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PcdSetBoolS (PcdPcie0HoldRstActive, FALSE);
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PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
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PcdSet32S (PcdPcie0PwrEnableGpioNo, GPIO_CNL_LP_GPP_C14);
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PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
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PcdSet8S (PcdPcie1GpioSupport, NotSupported);
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PcdSet32S (PcdPcie1WakeGpioNo, 0);
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PcdSet8S (PcdPcie1HoldRstExpanderNo, 0);
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PcdSet32S (PcdPcie1HoldRstGpioNo, 0);
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PcdSetBoolS (PcdPcie1HoldRstActive, FALSE);
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PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0);
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PcdSet32S (PcdPcie1PwrEnableGpioNo, 0);
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PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE);
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PcdSet8S (PcdPcie2GpioSupport, NotSupported);
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PcdSet32S (PcdPcie2WakeGpioNo, 0);
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PcdSet8S (PcdPcie2HoldRstExpanderNo, 0);
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PcdSet32S (PcdPcie2HoldRstGpioNo, 0);
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PcdSetBoolS (PcdPcie2HoldRstActive, FALSE);
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PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0);
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PcdSet32S (PcdPcie2PwrEnableGpioNo, 0);
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PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE);
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break;
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default:
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PcdSet8S(PcdRootPortIndex, 0xFF);
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PcdSet8S (PcdPcie0GpioSupport, NotSupported);
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PcdSet32S (PcdPcie0WakeGpioNo, 0);
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PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
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PcdSet32S (PcdPcie0HoldRstGpioNo, 0);
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PcdSetBoolS (PcdPcie0HoldRstActive, FALSE);
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PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
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PcdSet32S (PcdPcie0PwrEnableGpioNo, 0);
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PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
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PcdSet8S (PcdPcie1GpioSupport, NotSupported);
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PcdSet32S (PcdPcie1WakeGpioNo, 0);
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PcdSet8S (PcdPcie1HoldRstExpanderNo, 0);
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PcdSet32S (PcdPcie1HoldRstGpioNo, 0);
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PcdSetBoolS (PcdPcie1HoldRstActive, FALSE);
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PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0);
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PcdSet32S (PcdPcie1PwrEnableGpioNo, 0);
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PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE);
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PcdSet8S (PcdPcie2GpioSupport, NotSupported);
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PcdSet32S (PcdPcie2WakeGpioNo, 0);
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PcdSet8S (PcdPcie2HoldRstExpanderNo, 0);
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PcdSet32S (PcdPcie2HoldRstGpioNo, 0);
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PcdSetBoolS (PcdPcie2HoldRstActive, FALSE);
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PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0);
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PcdSet32S (PcdPcie2PwrEnableGpioNo, 0);
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PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE);
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break;
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}
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return EFI_SUCCESS;
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}
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/**
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SA Display DDI configuration init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integer represent the board id.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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SaDisplayConfigInit (
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IN UINT16 BoardId
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)
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{
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//
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// Update Display DDI Config
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//
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switch (BoardId) {
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case BoardIdUpXtreme:
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PcdSet32S (PcdSaDisplayConfigTable, (UINTN) mUpXtremeRowDisplayDdiConfig);
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PcdSet16S (PcdSaDisplayConfigTableSize, sizeof (mUpXtremeRowDisplayDdiConfig));
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break;
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default:
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break;
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}
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return EFI_SUCCESS;
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}
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