/*++
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Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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Module Name:
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MiscProcessorCacheFunction.c
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Abstract:
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BIOS processor cache details.
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Misc. subclass type 7.
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SMBIOS type 7.
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--*/
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#include "CommonHeader.h"
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#include "MiscSubclassDriver.h"
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#include <Register/Cpuid.h>
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MISC_SMBIOS_TABLE_FUNCTION(MiscProcessorCache)
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{
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EFI_SMBIOS_HANDLE SmbiosHandle;
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SMBIOS_TABLE_TYPE7 *SmbiosRecord;
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EFI_CACHE_SRAM_TYPE_DATA CacheSramType;
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CHAR16 *SocketDesignation;
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CHAR8 *OptionalStrStart;
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UINTN SocketStrLen;
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STRING_REF TokenToGet;
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UINT32 SubIndex;
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CPUID_CACHE_PARAMS_EAX CacheParamsEax;
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CPUID_CACHE_PARAMS_EBX CacheParamsEbx;
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UINT32 RegisterEcx;
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CPUID_CACHE_PARAMS_EDX CacheParamsEdx;
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UINT8 SystemCacheType;
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UINTN Size;
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//
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// Memory Device Locator
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//
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TokenToGet = STRING_TOKEN (STR_SOCKET_DESIGNATION);
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SocketDesignation = SmbiosMiscGetString (TokenToGet);
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SocketStrLen = StrLen(SocketDesignation);
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if (SocketStrLen > SMBIOS_STRING_MAX_LENGTH) {
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return EFI_UNSUPPORTED;
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}
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//
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// Retrieve cache level information using CPUID
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//
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for (SubIndex = 0; ; SubIndex++) {
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AsmCpuidEx (
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CPUID_CACHE_PARAMS,
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SubIndex,
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&CacheParamsEax.Uint32,
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&CacheParamsEbx.Uint32,
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&RegisterEcx,
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&CacheParamsEdx.Uint32
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);
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//
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// Terminate loop when CacheType is CPUID_CACHE_PARAMS_CACHE_TYPE_NULL
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//
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if (CacheParamsEax.Bits.CacheType == CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) {
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break;
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}
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//
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// Allocate and zero SMBIOS TYPE 7 Record
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//
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SmbiosRecord = AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);
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ASSERT (SmbiosRecord != NULL);
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//
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// Compute cache size in bytes
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//
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Size = (CacheParamsEbx.Bits.Ways + 1) *
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(CacheParamsEbx.Bits.LinePartitions + 1) *
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(CacheParamsEbx.Bits.LineSize + 1) *
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(RegisterEcx + 1);
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DEBUG ((DEBUG_INFO, "MiscProcessorCache(): Cache Type = %d Cache Level = %d Size = %x\n", CacheParamsEax.Bits.CacheType, CacheParamsEax.Bits.CacheLevel, Size));
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//
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// Determine SMBIOS SystemCacheType
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//
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switch (CacheParamsEax.Bits.CacheType) {
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case 1:
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SystemCacheType = CacheTypeData;
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break;
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case 2:
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SystemCacheType = CacheTypeInstruction;
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break;
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case 3:
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SystemCacheType = CacheTypeUnified;
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break;
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default:
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SystemCacheType = CacheTypeUnknown;
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}
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//
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// Update cache sizes in KB
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//
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switch (CacheParamsEax.Bits.CacheLevel) {
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case 1:
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SmbiosRecord->InstalledSize = (UINT16)(Size >> 10);
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SmbiosRecord->MaximumCacheSize = SmbiosRecord->InstalledSize;
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SmbiosRecord->SystemCacheType = SystemCacheType;
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SmbiosRecord->Associativity = CacheAssociativity8Way;
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SmbiosRecord->CacheConfiguration = 0x0180;
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break;
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case 2:
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SmbiosRecord->InstalledSize = (UINT16)(Size >> 10);
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SmbiosRecord->MaximumCacheSize = SmbiosRecord->InstalledSize;
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SmbiosRecord->SystemCacheType = SystemCacheType;
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SmbiosRecord->Associativity = CacheAssociativity16Way;
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SmbiosRecord->CacheConfiguration = 0x0281;
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//
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//VLV2 incorporates two SLM modules (quad cores) in the SoC.
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// 2 cores share BIU/L2 cache
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//
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SmbiosRecord->InstalledSize = SmbiosRecord->InstalledSize / 2;
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SmbiosRecord->MaximumCacheSize = SmbiosRecord->InstalledSize;
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break;
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default:
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DEBUG ((DEBUG_ERROR, "MiscProcessorCache(): Unexpected cache level %d\n", CacheParamsEax.Bits.CacheLevel));
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break;
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}
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//
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//Filling SMBIOS type 7 information for different cache levels.
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//
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SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_CACHE_INFORMATION;
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SmbiosRecord->Hdr.Length = (UINT8) sizeof (SMBIOS_TABLE_TYPE7);
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SmbiosRecord->Hdr.Handle = 0;
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SmbiosRecord->SocketDesignation = 0x01;
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SmbiosRecord->CacheSpeed = 0;
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ZeroMem (&CacheSramType, sizeof (EFI_CACHE_SRAM_TYPE_DATA));
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CacheSramType.Synchronous = 1;
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CopyMem(&SmbiosRecord->SupportedSRAMType, &CacheSramType, 2);
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CopyMem(&SmbiosRecord->CurrentSRAMType, &CacheSramType, 2);
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SmbiosRecord->ErrorCorrectionType = EfiCacheErrorSingleBit;
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//
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// Adding SMBIOS type 7 records to SMBIOS table.
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//
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SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
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OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
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UnicodeStrToAsciiStrS (SocketDesignation, OptionalStrStart, + 7 + 1 + 1);
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Smbios->Add(
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Smbios,
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NULL,
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&SmbiosHandle,
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(EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
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);
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}
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return EFI_SUCCESS;
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}
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