/** @file
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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Module Name:
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IchTcoReset.c
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Abstract:
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Implements the programming of events in TCO Reset
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--*/
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#include "PlatformDxe.h"
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#include <Protocol/TcoReset.h>
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#include <Protocol/HwWatchdogTimer.h>
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EFI_STATUS
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EFIAPI
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EnableTcoReset (
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IN UINT32 *RcrbGcsSaveValue
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);
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EFI_STATUS
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EFIAPI
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DisableTcoReset (
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OUT UINT32 RcrbGcsRestoreValue
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);
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EFI_TCO_RESET_PROTOCOL mTcoResetProtocol = {
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EnableTcoReset,
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DisableTcoReset
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};
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/**
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Enables the TCO timer to reset the system in case of a system hang. This is
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used when writing the clock registers.
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@param RcrbGcsSaveValue This is the value of the RCRB GCS register before it is
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changed by this procedure. This will be used to restore
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the settings of this register in PpiDisableTcoReset.
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@retval EFI_STATUS
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**/
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EFI_STATUS
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EFIAPI
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EnableTcoReset (
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IN UINT32 *RcrbGcsSaveValue
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)
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{
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UINT16 TmpWord;
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UINT16 AcpiBase;
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EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL *WatchdogTimerProtocol;
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EFI_STATUS Status;
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UINTN PbtnDisableInterval = 4; //Default value
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//
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// Get Watchdog Timer protocol.
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//
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Status = gBS->LocateProtocol (
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&gEfiWatchdogTimerDriverProtocolGuid,
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NULL,
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(VOID **)&WatchdogTimerProtocol
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);
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//
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// If the protocol is present, shut off the Timer as we enter BDS
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//
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if (!EFI_ERROR(Status)) {
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WatchdogTimerProtocol->RestartWatchdogTimer();
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WatchdogTimerProtocol->AllowKnownReset(TRUE);
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}
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if (*RcrbGcsSaveValue == 0) {
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PbtnDisableInterval = PcdGet32(PcdPBTNDisableInterval);
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} else {
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PbtnDisableInterval = *RcrbGcsSaveValue * 10 / 6;
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}
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//
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// Read ACPI Base Address
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//
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AcpiBase = PchLpcPciCfg16(R_PCH_LPC_ACPI_BASE) & B_PCH_LPC_ACPI_BASE_BAR;
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//
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// Stop TCO if not already stopped
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//
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TmpWord = IoRead16(AcpiBase + R_PCH_TCO_CNT);
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TmpWord |= B_PCH_TCO_CNT_TMR_HLT;
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IoWrite16(AcpiBase + R_PCH_TCO_CNT, TmpWord);
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//
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// Clear second TCO status
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//
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IoWrite32(AcpiBase + R_PCH_TCO_STS, B_PCH_TCO_STS_SECOND_TO);
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//
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// Enable reboot on TCO timeout
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//
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*RcrbGcsSaveValue = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG);
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MmioAnd8 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG, (UINT8) ~B_PCH_PMC_PM_CFG_NO_REBOOT);
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//
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// Set TCO reload value (interval *.6s)
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//
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IoWrite32(AcpiBase + R_PCH_TCO_TMR, (UINT32)(PbtnDisableInterval<<16));
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//
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// Force TCO to load new value
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//
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IoWrite8(AcpiBase + R_PCH_TCO_RLD, 4);
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//
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// Clear second TCO status
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//
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IoWrite32(AcpiBase + R_PCH_TCO_STS, B_PCH_TCO_STS_SECOND_TO);
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//
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// Start TCO timer running
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//
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TmpWord = IoRead16(AcpiBase + R_PCH_TCO_CNT);
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TmpWord &= ~(B_PCH_TCO_CNT_TMR_HLT);
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IoWrite16(AcpiBase + R_PCH_TCO_CNT, TmpWord);
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return EFI_SUCCESS;
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}
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/**
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Disables the TCO timer. This is used after writing the clock registers.
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@param RcrbGcsRestoreValue Value saved in PpiEnableTcoReset so that it can
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restored.
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@retval EFI_STATUS
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**/
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EFI_STATUS
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EFIAPI
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DisableTcoReset (
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OUT UINT32 RcrbGcsRestoreValue
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)
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{
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UINT16 TmpWord;
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UINT16 AcpiBase;
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EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL *WatchdogTimerProtocol;
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EFI_STATUS Status;
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//
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// Read ACPI Base Address
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//
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AcpiBase = PchLpcPciCfg16(R_PCH_LPC_ACPI_BASE) & B_PCH_LPC_ACPI_BASE_BAR;
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//
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// Stop the TCO timer
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//
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TmpWord = IoRead16(AcpiBase + R_PCH_TCO_CNT);
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TmpWord |= B_PCH_TCO_CNT_TMR_HLT;
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IoWrite16(AcpiBase + R_PCH_TCO_CNT, TmpWord);
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//
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// Get Watchdog Timer protocol.
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//
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Status = gBS->LocateProtocol (
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&gEfiWatchdogTimerDriverProtocolGuid,
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NULL,
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(VOID **)&WatchdogTimerProtocol
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);
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//
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// If the protocol is present, shut off the Timer as we enter BDS
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//
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if (!EFI_ERROR(Status)) {
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WatchdogTimerProtocol->AllowKnownReset(FALSE);
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}
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return EFI_SUCCESS;
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}
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/**
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Updates the feature policies according to the setup variable.
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@retval Returns VOID
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**/
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VOID
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InitTcoReset (
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)
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{
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EFI_HANDLE Handle;
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EFI_STATUS Status;
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Handle = NULL;
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Status = gBS->InstallProtocolInterface (
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&Handle,
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&gEfiTcoResetProtocolGuid,
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EFI_NATIVE_INTERFACE,
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&mTcoResetProtocol
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);
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ASSERT_EFI_ERROR(Status);
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}
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