/** @file
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This file describes the contents of the ACPI Fixed ACPI Description Table
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(FADT). Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.
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All changes to the FADT contents should be done in this file.
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Copyright (c) 2013-2015 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "Fadt.h"
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EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = {
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EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
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sizeof (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE),
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EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
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0, // to make sum of entire table == 0
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EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field
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EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)
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EFI_ACPI_OEM_REVISION, // OEM revision number
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EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID
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EFI_ACPI_CREATOR_REVISION, // ASL compiler revision number
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0, // Physical addesss of FACS
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0, // Physical address of DSDT
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INT_MODEL, // System Interrupt Model
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RESERVED, // reserved
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SCI_INT_VECTOR, // System vector of SCI interrupt
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SMI_CMD_IO_PORT, // Port address of SMI command port
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ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI
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ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI
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S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state
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RESERVED, // reserved - must be zero
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PM1a_EVT_BLK_ADDRESS, // Port address of Power Mgt 1a Event Reg Blk
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PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk
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PM1a_CNT_BLK_ADDRESS, // Port address of Power Mgt 1a Ctrl Reg Blk
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PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk
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PM2_CNT_BLK_ADDRESS, // Port address of Power Mgt 2 Ctrl Reg Blk
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PM_TMR_BLK_ADDRESS, // Port address of Power Mgt Timer Ctrl Reg Blk
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GPE0_BLK_ADDRESS, // Port addr of General Purpose Event 0 Reg Blk
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GPE1_BLK_ADDRESS, // Port addr of General Purpose Event 1 Reg Blk
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PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk
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PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk
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PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk
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PM_TM_LEN, // Byte Length of ports at pm_tm_blk
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GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk
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GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk
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GPE1_BASE, // offset in gpe model where gpe1 events start
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RESERVED, // reserved
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P_LVL2_LAT, // worst case HW latency to enter/exit C2 state
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P_LVL3_LAT, // worst case HW latency to enter/exit C3 state
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FLUSH_SIZE, // Size of area read to flush caches
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FLUSH_STRIDE, // Stride used in flushing caches
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DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg
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DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg
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DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM
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MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM
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CENTURY, // index to century in RTC CMOS RAM
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RESERVED, // reserved
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RESERVED, // reserved
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RESERVED, // reserved
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FLAG
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};
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VOID*
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ReferenceAcpiTable (
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VOID
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)
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{
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//
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// Reference the table being generated to prevent the optimizer from removing the
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// data structure from the exeutable
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//
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return (VOID*)&FADT;
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}
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