/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _EFI_GLOBAL_NVS_AREA_H_
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#define _EFI_GLOBAL_NVS_AREA_H_
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//
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// Global NVS Area definition
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//
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#pragma pack (1)
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typedef struct {
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// IOAPIC Start
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UINT32 PlatformId;
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UINT32 IoApicEnable;
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UINT8 ApicIdOverrided :1;
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UINT8 RES0 :7;
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// IOAPIC End
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// Power Management Start
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UINT8 Rsvd_Pms_0 :1;
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UINT8 CStateEnable :1;
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UINT8 C3Enable :1;
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UINT8 C6Enable :1;
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UINT8 C7Enable :1;
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UINT8 MonitorMwaitEnable :1;
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UINT8 PStateEnable :1;
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UINT8 EmcaEn :1;
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UINT8 HWAllEnable :2;
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UINT8 KBPresent :1;
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UINT8 MousePresent :1;
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UINT8 TStateEnable :1;
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UINT8 TStateFineGrained: 1;
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UINT8 OSCX :1;
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UINT8 RESX :1;
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// Power Management End
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// RAS Start
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UINT8 CpuChangeMask;
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UINT8 IioChangeMask;
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UINT64 IioPresentBitMask;
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UINT32 SocketBitMask; //make sure this is at 4byte boundary
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UINT32 ProcessorApicIdBase[8];
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UINT64 ProcessorBitMask[8];
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UINT16 MemoryBoardBitMask;
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UINT16 MemoryBoardChgEvent;
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UINT32 MmCfg;
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UINT32 TsegSize;
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UINT64 MemoryBoardBase[8];
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UINT64 MemoryBoardRange[8];
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UINT32 SmiRequestParam[4];
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UINT32 SciRequestParam[4];
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UINT64 MigrationActionRegionAddress;
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UINT8 Cpu0Uuid[16];
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UINT8 Cpu1Uuid[16];
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UINT8 Cpu2Uuid[16];
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UINT8 Cpu3Uuid[16];
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UINT8 Cpu4Uuid[16];
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UINT8 Cpu5Uuid[16];
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UINT8 Cpu6Uuid[16];
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UINT8 Cpu7Uuid[16];
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UINT8 CpuSpareMask;
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UINT8 Mem0Uuid[16];
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UINT8 Mem1Uuid[16];
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UINT8 Mem2Uuid[16];
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UINT8 Mem3Uuid[16];
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UINT8 Mem4Uuid[16];
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UINT8 Mem5Uuid[16];
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UINT8 Mem6Uuid[16];
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UINT8 Mem7Uuid[16];
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UINT8 Mem8Uuid[16];
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UINT8 Mem9Uuid[16];
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UINT8 Mem10Uuid[16];
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UINT8 Mem11Uuid[16];
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UINT8 Mem12Uuid[16];
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UINT8 Mem13Uuid[16];
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UINT8 Mem14Uuid[16];
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UINT8 Mem15Uuid[16];
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UINT16 MemSpareMask;
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UINT64 EmcaL1DirAddr;
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UINT32 ProcessorId;
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UINT8 PcieAcpiHotPlugEnable;
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// RAS End
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// VTD Start
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UINT64 DrhdAddr[3];
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UINT64 AtsrAddr[3];
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UINT64 RhsaAddr[3];
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// VTD End
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// BIOS Guard Start
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UINT8 CpuSkuNumOfBitShift;
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// BIOS Guard End
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// USB3 Start
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UINT8 XhciMode;
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UINT8 HostAlertVector1;
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UINT8 HostAlertVector2;
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// USB3 End
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// HWPM Start
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UINT8 HWPMEnable:2; //HWPM
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UINT8 AutoCstate:1; //HWPM
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UINT8 HwpInterrupt:1; //HWP Interrupt
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UINT8 RES1:4; //reserved bits
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// HWPM End
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// PCIe Multi-Seg Start
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// for 8S support needs max 32 IIO IOxAPIC being enabled!
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UINT8 BusBase[48]; // MAX_SOCKET * MAX_IIO_STACK. Note: hardcode due to ASL constraint.
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UINT8 PCIe_MultiSeg_Support; // Enable /Disable switch
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// for 8S support needs matching to MAX_SOCKET!
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UINT8 PcieSegNum[8]; // Segment number array. Must match MAX_SOCKET. Note: hardcode due to ASL constraint.
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// PCIe Multi-seg end
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// Performance Start
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UINT8 SncAnd2Cluster; //1=SncEn and NumCluster=2, otherwise 0
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// Performance End
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} BIOS_ACPI_PARAM;
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#pragma pack ()
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#endif
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