## @file
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#
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# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2021, American Megatrends International LLC.<BR>
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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################################################################################
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#
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# Pcd Section - list of all PCD Entries defined by this board.
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#
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################################################################################
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[PcdsFixedAtBuild.common]
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######################################
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# Key Boot Stage and FSP configuration
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######################################
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#
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# Please select the Boot Stage here.
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# Stage 1 - enable debug (system deadloop after debug init)
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# Stage 2 - mem init (system deadloop after mem init)
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# Stage 3 - boot to shell only
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# Stage 4 - boot to OS
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# Stage 5 - boot to OS with security boot enabled
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# Stage 6 - boot with advanced features enabled
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#
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gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
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[PcdsFeatureFlag.common]
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gPlatformTokenSpaceGuid.PcdLockCsrSsidSvidRegister|FALSE
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# Server doesn't support capsle update on Reset.
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gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE
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gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE
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gEfiCpuTokenSpaceGuid.PcdCpuHotPlugSupport|TRUE
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gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|TRUE
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gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE
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#S3 add
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gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
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#S3 add
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gEfiCpuTokenSpaceGuid.PcdCpuConroeFamilyFlag|FALSE
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gEfiCpuTokenSpaceGuid.PcdCpuCedarMillFamilyFlag|FALSE
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gEfiCpuTokenSpaceGuid.PcdCpuPrescottFamilyFlag|FALSE
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gEfiCpuTokenSpaceGuid.PcdCpuNehalemFamilyFlag|FALSE
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gEfiCpuTokenSpaceGuid.PcdCpuIvyBridgeFamilyFlag|FALSE
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gEfiCpuTokenSpaceGuid.PcdCpuSandyBridgeFamilyFlag|FALSE
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gEfiCpuTokenSpaceGuid.PcdCpuHaswellFamilyFlag|TRUE
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gEfiCpuTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|TRUE
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gEfiCpuTokenSpaceGuid.PcdCpuGateA20MDisableFlag|FALSE
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gEfiCpuTokenSpaceGuid.PcdCpuSmmDebug|TRUE
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gEfiCpuTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE
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gEfiCpuTokenSpaceGuid.PcdCpuSocketIdReassignmentFlag|TRUE
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## This PCD specified whether ACPI SDT protocol is installed.
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gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
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######################################
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# Platform Configuration
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######################################
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gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|TRUE
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gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|FALSE
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
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gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
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gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
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!endif
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!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
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gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
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gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
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!endif
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!if $(TARGET) == DEBUG
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gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
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!else
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gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
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!endif
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[PcdsFeatureFlag.X64]
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE
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[PcdsFeatureFlag]
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gEfiMdeModulePkgTokenSpaceGuid.PcdBrowerGrayOutReadOnlyMenu|TRUE
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gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable|TRUE
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gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable|TRUE
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gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable|TRUE
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[PcdsDynamicExDefault]
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!include $(PROJECT)/StructureConfig.dsc
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[PcdsFixedAtBuild.X64]
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gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x01, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x01, 0x01, 0x01, 0x06, 0x00, 0x00, 0x01, 0x7F, 0xFF, 0x04, 0x00}
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[PcdsFixedAtBuild.IA32]
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gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0x00FFA00000
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gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x0000600000
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[PcdsFixedAtBuild.common]
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gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRUE
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!if $(TARGET) == "RELEASE"
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gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
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gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03
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!else
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gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
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gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
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!endif
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!if $(TARGET) == RELEASE
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gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
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!else
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gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
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!endif
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gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
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gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0
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gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
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#S3 modified
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gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000
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gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE
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#S3 modified
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gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
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gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0
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gEfiMdePkgTokenSpaceGuid.PcdFSBClock|133333333
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gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000
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gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x1700000
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gEfiCpuTokenSpaceGuid.PcdCpuIEDRamSize|0x400000
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gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
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gEfiCpuTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
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gEfiCpuTokenSpaceGuid.PcdPlatformType|2
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gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|4000
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gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxFsbFrequency|1066
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gEfiCpuTokenSpaceGuid.PcdCpuSmmStackSize|0x10000
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000
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## Specifies delay value in microseconds after sending out an INIT IPI.
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# @Prompt Configure delay value after send an INIT IPI
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gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10
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## Specifies max supported number of Logical Processors.
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# @Prompt Configure max supported number of Logical Processorss
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000
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!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
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gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
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!endif
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gPlatformTokenSpaceGuid.PcdBusStack|0x06
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gPlatformTokenSpaceGuid.PcdUboDev|0x08
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gPlatformTokenSpaceGuid.PcdUboFunc|0x02
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gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC
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gEfiCpuTokenSpaceGuid.PcdCpuIEDEnabled|TRUE
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## Defines the ACPI register set base address.
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# The invalid 0xFFFF is as its default value. It must be configured to the real value.
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# @Prompt ACPI Timer IO Port Address
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x0500
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## Defines the PCI Bus Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
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# @Prompt ACPI Hardware PCI Bus Number
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00
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gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002
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gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49
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gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x20091013
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## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
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# The invalid 0xFF is as its default value. It must be configured to the real value.
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# @Prompt ACPI Hardware PCI Device Number
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F
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## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
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# The invalid 0xFF is as its default value. It must be configured to the real value.
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# @Prompt ACPI Hardware PCI Function Number
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x02
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## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers.
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# The invalid 0xFFFF is as its default value. It must be configured to the real value.
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# @Prompt ACPI Hardware PCI Register Offset
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044
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## Defines the bit mask that must be set to enable the APIC hardware register BAR.
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# @Prompt ACPI Hardware PCI Bar Enable BitMask
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80
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## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers.
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# The invalid 0xFFFF is as its default value. It must be configured to the real value.
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# @Prompt ACPI Hardware PCI Bar Register Offset
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040
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## Defines the offset to the 32-bit Timer Value register that resides within the ACPI BAR.
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# @Prompt Offset to 32-bit Timer register in ACPI BAR
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008
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## Defines the bit mask to retrieve ACPI IO Port Base Address
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# @Prompt ACPI IO Port Base Address Mask
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gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask |0xFFFC
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# Indicates the max nested level
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gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel|0x00000010
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gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET)
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gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET)
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gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|28
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gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x70
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x80
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x1470
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0xA0
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gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x80
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#
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# The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
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#
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# BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions.
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# BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \
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# that lie entirely within the expected fixed memory regions.
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# BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms.
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# BIT3-31: Reserved
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#
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gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
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[PcdsFixedAtBuild.X64]
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gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2015
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gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2099
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# Change PcdBootManagerMenuFile to UiApp
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##
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gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
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gEfiCpuTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE
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gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x04
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gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000
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gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5
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gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xA0
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gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xA1
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gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000
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gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000
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gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x08
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gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|32
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gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09
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gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000
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gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24
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gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x500
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gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0
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gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x504
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gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0
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gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x550
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gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x508
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gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x580
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gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0
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[PcdsPatchableInModule.common]
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gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000042
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!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
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gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
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!endif
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gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000
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gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
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gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000
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gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase |0x1000
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gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit |0xFFFF
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gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase |0x90000000
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gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit |0xFBFFFFFF
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gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase |0x380000000000
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gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit |0x3803FFFFFFFF
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gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
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gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
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gEfiCpuTokenSpaceGuid.PcdCpuSmmUseDelayIndication|FALSE
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gEfiCpuTokenSpaceGuid.PcdCpuSmmUseBlockIndication|FALSE
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gEfiCpuTokenSpaceGuid.PcdCpuSmmUseSmmEnableIndication|FALSE
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gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE
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gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000
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gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize|0x01400000
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[PcdsDynamicExDefault.common.DEFAULT]
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gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfiguration|0x002CF6CF
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gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfigurationEx1|0
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|30000
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gEfiCpuTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|200000
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gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE
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gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0
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gEfiPchTokenSpaceGuid.PcdWakeOnRTCS5|FALSE
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gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeHour|0
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gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeMinute|0
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gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeSecond|0
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gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex|0x5
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[PcdsDynamicExHii.common.DEFAULT]
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!if gPlatformTokenSpaceGuid.PcdFastBoot == FALSE
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gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|3 # Variable: L"Timeout"
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!else
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gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|0 # Variable: L"Timeout"
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!endif
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gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
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|
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[PcdsDynamicExDefault]
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gOemSkuTokenSpaceGuid.PcdForceTo1SConfigMode|FALSE
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## *** PURLEY_PPO *** - Added in 8th segment in PcdPcieMmcfgTablePtr to fix size assert in PcieAddressLib.c
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## | MMCFG Table Header | Segment 0 | Segment 1 | Segment 2 | Segment 3 | Segment 4 | Segment 5 | Segment 6 | Segment 7 | Segment 8
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gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr|{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}
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gEfiCpuTokenSpaceGuid.PcdCpuEnergyPolicy|0
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gEfiCpuTokenSpaceGuid.PcdCpuAcpiLvl2Addr|0
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gEfiCpuTokenSpaceGuid.PcdCpuPackageCStateLimit|0
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gEfiCpuTokenSpaceGuid.PcdCpuCoreCStateValue|0
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gEfiCpuTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0
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gEfiCpuTokenSpaceGuid.PcdCpuHwCoordination|TRUE
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gEfiCpuTokenSpaceGuid.PcdCpuDcuMode|0
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gEfiCpuTokenSpaceGuid.PcdCpuTurboOverride|0x0
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gEfiCpuTokenSpaceGuid.PcdCpuProcessorMsrLockCtrl|0
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gEfiCpuTokenSpaceGuid.PcdCpuIioLlcWaysBitMask|0x0
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gEfiCpuTokenSpaceGuid.PcdCpuExpandedIioLlcWaysBitMask|0x0
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gEfiCpuTokenSpaceGuid.PcdCpuRemoteWaysBitMask|0x0
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gEfiCpuTokenSpaceGuid.PcdPchTraceHubEn|0x0
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gEfiCpuTokenSpaceGuid.PcdCpuQlruCfgBitMask|0x0
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gEfiCpuTokenSpaceGuid.PcdSbspSelection|0xFF
|
# gEfiCpuTokenSpaceGuid.PcdCpuSocketId|{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x1,0x0,0x0,0x0,0x1,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x3,0x0,0x0,0x0}
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gEfiCpuTokenSpaceGuid.PcdCpuPmStructAddr|0x0
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gEfiCpuTokenSpaceGuid.PcdCpuRRQCountThreshold|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|TRUE
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gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE
|
gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE
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gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x1F
|
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gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L""|VOID*|36
|
|
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|{0x49, 0x4E, 0x54, 0x45, 0x4C, 0x20}
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gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x2046573030363253
|
|
gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0
|
|
[PcdsDynamicExDefault.X64]
|
|
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
|
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
|
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
|
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
|
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0
|
|
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
|
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
|
|
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800
|
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600
|
|
gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0
|
