/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2021, American Megatrends International LLC.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/SerialPortLib.h>
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#include <Library/DebugLib.h>
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#define R_ICH_IOPORT_PCI_INDEX 0xCF8
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#define R_ICH_IOPORT_PCI_DATA 0xCFC
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#define R_ICH_LPC_IO_DEC 0x80
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#define PCI_DEVICE_NUMBER_ICH_LPC 31
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#define PCI_FUNCTION_NUMBER_ICH_LPC 0
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#define PCI_CF8_ADDR(Bus, Dev, Func, Off) \
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(((Off) & 0xFF) | (((Func) & 0x07) << 8) | (((Dev) & 0x1F) << 11) | (((Bus) & 0xFF) << 16) | (1 << 31))
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#define ICH_LPC_CF8_ADDR(Offset) PCI_CF8_ADDR(0, PCI_DEVICE_NUMBER_ICH_LPC, PCI_FUNCTION_NUMBER_ICH_LPC, Offset)
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#include "SioRegs.h"
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//
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// ---------------------------------------------
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// Additional SIO Regs for Tioga Pass
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// ---------------------------------------------
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//
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#define SCU_BASE 0x1E6E2000
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#include <Platform.h>
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#include <PchAccess.h>
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//
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// ---------------------------------------------
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// UART Register Offsets
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// ---------------------------------------------
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//
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#define BAUD_LOW_OFFSET 0x00
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#define BAUD_HIGH_OFFSET 0x01
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#define IER_OFFSET 0x01
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#define LCR_SHADOW_OFFSET 0x01
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#define FCR_SHADOW_OFFSET 0x02
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#define IR_CONTROL_OFFSET 0x02
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#define FCR_OFFSET 0x02
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#define EIR_OFFSET 0x02
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#define BSR_OFFSET 0x03
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#define LCR_OFFSET 0x03
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#define MCR_OFFSET 0x04
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#define LSR_OFFSET 0x05
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#define MSR_OFFSET 0x06
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//
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// ---------------------------------------------
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// UART Register Bit Defines
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// ---------------------------------------------
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//
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#define LSR_TXRDY 0x20
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#define LSR_RXDA 0x01
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#define DLAB 0x01
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#define UART_DATA 8
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#define UART_STOP 1
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#define UART_PARITY 0
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#define UART_BREAK_SET 0
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UINT16 gComBase = 0x3f8;
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UINTN gBps = 115200;
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UINT8 gData = 8;
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UINT8 gStop = 1;
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UINT8 gParity = 0;
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UINT8 gBreakSet = 0;
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/**
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Write AHB register.
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@param RegIndex: register index.
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@param Value: Value to write
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@retval None.
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**/
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VOID
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WriteAHBDword(
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UINT32 RegIndex,
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UINT32 Value
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)
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{
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UINT8 bValue;
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IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK);
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IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK);
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IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_DATA_PORT, SIO_SMI);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_INDEX_PORT, 0x30);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_DATA_PORT, 1);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_INDEX_PORT, 0xf8);
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bValue = IoRead8(SIO_DATA_PORT);
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bValue &= 0xfc;
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bValue |= 2; // 4 byte window.
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IoWrite8 (SIO_DATA_PORT, bValue);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_INDEX_PORT, 0xf0);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 24)& 0xff));
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IoWrite8 (SIO_INDEX_PORT, 0xf1);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 16)& 0xff));
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IoWrite8 (SIO_INDEX_PORT, 0xf2);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 8) & 0xff));
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IoWrite8 (SIO_INDEX_PORT, 0xf3);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex )& 0xff));
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IoWrite8 (SIO_INDEX_PORT, 0xf4);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_DATA_PORT, (UINT8)((Value >> 24)& 0xff));
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IoWrite8 (SIO_INDEX_PORT, 0xf5);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_DATA_PORT, (UINT8)((Value >> 16)& 0xff));
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IoWrite8 (SIO_INDEX_PORT, 0xf6);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_DATA_PORT, (UINT8)((Value >> 8) & 0xff));
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IoWrite8 (SIO_INDEX_PORT, 0xf7);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_DATA_PORT, (UINT8)((Value )& 0xff));
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// trigger write
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IoWrite8 (SIO_INDEX_PORT, 0xfe);
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IoWrite8 (SIO_DATA_PORT, 0xcf);
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IoWrite8 (SIO_INDEX_PORT, SIO_LOCK);
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}
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/**
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Read AHB register.
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@param RegIndex: register index.
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@retval value of register.
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**/
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UINT32
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ReadAHBDword(
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UINT32 RegIndex
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){
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UINT8 bValue;
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UINT32 rdValue = 0;
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IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK);
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IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK);
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IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_DATA_PORT, SIO_SMI);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_INDEX_PORT, 0x30);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_DATA_PORT, 1);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_INDEX_PORT, 0xf8);
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bValue = IoRead8(SIO_DATA_PORT);
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bValue &= 0xfc;
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bValue |= 2; // 4 byte window.
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IoWrite8 (SIO_DATA_PORT, bValue);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_INDEX_PORT, 0xf0);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 24)& 0xff));
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IoWrite8 (SIO_INDEX_PORT, 0xf1);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 16)& 0xff));
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IoWrite8 (SIO_INDEX_PORT, 0xf2);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 8) & 0xff));
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IoWrite8 (SIO_INDEX_PORT, 0xf3);
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IoWrite8 (0xED, 0);//short delay.
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IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex )& 0xff));
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// trigger read
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IoWrite8 (SIO_INDEX_PORT, 0xfe);
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IoRead8 (SIO_DATA_PORT);
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IoWrite8 (SIO_INDEX_PORT, 0xf4);
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rdValue += IoRead8 (SIO_DATA_PORT);
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rdValue <<= 8;
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IoWrite8 (SIO_INDEX_PORT, 0xf5);
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rdValue += IoRead8 (SIO_DATA_PORT);
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rdValue <<= 8;
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IoWrite8 (SIO_INDEX_PORT, 0xf6);
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rdValue += IoRead8 (SIO_DATA_PORT);
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rdValue <<= 8;
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IoWrite8 (SIO_INDEX_PORT, 0xf7);
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rdValue += IoRead8 (SIO_DATA_PORT);
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IoWrite8 (SIO_INDEX_PORT, SIO_LOCK);
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return rdValue;
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}
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/**
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Initialize the AST2500 SIO.
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@param None
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@retval None
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**/
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VOID
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InitializeSio (
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VOID
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)
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{
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UINT32 Decode;
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UINT32 Enable;
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UINT32 Value;
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UINT32 Address;
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//
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// Enable LPC decode
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// Set COMA/COMB base
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//
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Decode = ((V_PCH_LPC_IOD_COMA_3F8 << N_PCH_LPC_IOD_COMA) | (V_PCH_LPC_IOD_COMB_2F8 << N_PCH_LPC_IOD_COMB));
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Enable = ( B_PCH_LPC_IOE_ME2 | B_PCH_LPC_IOE_SE | B_PCH_LPC_IOE_ME1 \
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| B_PCH_LPC_IOE_KE | B_PCH_LPC_IOE_CBE | B_PCH_LPC_IOE_CAE);
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IoWrite32 (R_ICH_IOPORT_PCI_INDEX, (UINT32) (ICH_LPC_CF8_ADDR (R_ICH_LPC_IO_DEC)));
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IoWrite32 (R_ICH_IOPORT_PCI_DATA, Decode | (Enable << 16));
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MmioWrite16 (PCH_PCR_ADDRESS(PID_DMI, R_PCH_PCR_DMI_LPCIOD), (UINT16)Decode);
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MmioWrite16 (PCH_PCR_ADDRESS(PID_DMI, R_PCH_PCR_DMI_LPCIOE), (UINT16)Enable);
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IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK);
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IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK);
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//
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// Initialize COM1
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//
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IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE);
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IoWrite8 (SIO_DATA_PORT, SIO_UART1);
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IoWrite8 (SIO_INDEX_PORT, ACTIVATE);
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IoWrite8 (SIO_DATA_PORT, 0);
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IoWrite8 (SIO_INDEX_PORT, 0x70);
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IoWrite8 (SIO_DATA_PORT, 0x04);
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//
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// Set Base Address to gComBase
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//
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IoWrite8 (SIO_INDEX_PORT, BASE_ADDRESS_LOW0);
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IoWrite8 (SIO_DATA_PORT, (UINT8) (gComBase & 0xFF));
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IoWrite8 (SIO_INDEX_PORT, BASE_ADDRESS_HIGH0);
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IoWrite8 (SIO_DATA_PORT, (UINT8)((gComBase >> 8) & 0xff));
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//
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// Activate COM1
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//
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IoWrite8 (SIO_INDEX_PORT, ACTIVATE);
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IoWrite8 (SIO_DATA_PORT, 1);
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IoWrite8 (SIO_INDEX_PORT, SIO_LOCK);
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// Initialize SCU part.
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Address = (UINT32)(SCU_BASE | 0x00);
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Value = ReadAHBDword(Address);
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Value &= 0x00000000;
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Value |= 0x1688A8A8; // Unlock SCU Registers
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WriteAHBDword(Address,Value);
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Address = (UINT32)(SCU_BASE | 0x84);
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Value = ReadAHBDword(Address);
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Value &= 0xFF3FFFFF;
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Value |= 0x00C00000; // SCU84[23:22]="11b" Enable UART1 or video VPB Multi-Function pins
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WriteAHBDword(Address,Value);
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Address = (UINT32)(SCU_BASE | 0x90);
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Value = ReadAHBDword(Address);
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Value &= 0xFFFFFFDF;
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Value |= 0x00000000; // SCU90[5]="0b" Disable digital video Multi-Function pins
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WriteAHBDword(Address,Value);
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Address = (UINT32)(SCU_BASE | 0x94);
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Value = ReadAHBDword(Address);
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Value &= 0xFFFFFFFC;
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Value |= 0x00000000; // SCU94[1:0]="00b" Disable digital video Multi-Function pins
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WriteAHBDword(Address,Value);
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Address = (UINT32)(SCU_BASE | 0x00);
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Value = ReadAHBDword(Address);
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Value &= 0x00000000;
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Value |= 0x00000000; // Lock SCU Registers
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WriteAHBDword(Address,Value);
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}
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/**
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Performs platform specific initialization required for the CPU to access
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the hardware associated with a SerialPortLib instance. This function does
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not initialize the serial port hardware itself. Instead, it initializes
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hardware devices that are required for the CPU to access the serial port
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hardware. This function may be called more than once.
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@retval RETURN_SUCCESS The platform specific initialization succeeded.
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@retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.
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**/
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RETURN_STATUS
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EFIAPI
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PlatformHookSerialPortInitialize (
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VOID
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)
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{
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UINTN Divisor;
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UINT8 OutputData;
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UINT8 Data;
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InitializeSio();
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//
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// Some init is done by the platform status code initialization.
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//
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//
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// Map 5..8 to 0..3
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//
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Data = (UINT8) (gData - (UINT8) 5);
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//
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// Calculate divisor for baud generator
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//
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Divisor = 115200 / gBps;
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//
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// Set communications format
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//
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OutputData = (UINT8) ((DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));
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IoWrite8 (gComBase + LCR_OFFSET, OutputData);
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//
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// Configure baud rate
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//
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IoWrite8 (gComBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8));
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IoWrite8 (gComBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff));
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//
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// Switch back to bank 0
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//
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OutputData = (UINT8) ((~DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));
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IoWrite8 (gComBase + LCR_OFFSET, OutputData);
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return RETURN_SUCCESS;
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}
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