/** @file
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Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiPei.h>
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#include <SaPolicyCommon.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/IoLib.h>
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#include <Library/HobLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/PciLib.h>
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#include <Library/PcdLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/PeiSaPolicyLib.h>
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#include <Library/BoardInitLib.h>
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#include <PchAccess.h>
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#include <Library/GpioNativeLib.h>
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#include <Library/GpioLib.h>
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#include <GpioPinsSklLp.h>
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#include <GpioPinsSklH.h>
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#include <Library/GpioExpanderLib.h>
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#include <SioRegs.h>
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#include <Library/PchPcrLib.h>
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#include <Library/SiliconInitLib.h>
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#include <Library/PchResetLib.h>
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#include "PeiKabylakeRvp3InitLib.h"
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#include <ConfigBlock.h>
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#include <ConfigBlock/MemoryConfig.h>
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//
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// Reference RCOMP resistors on motherboard - for SKL RVP1
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//
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GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX_RCOMP] = { 200, 81, 162 };
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//
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// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SKL RVP1
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//
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GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 };
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/**
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SkylaeA0Rvp3 board configuration init function for PEI pre-memory phase.
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PEI_BOARD_CONFIG_PCD_INIT
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@param Content pointer to the buffer contain init information for board init.
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@retval EFI_SUCCESS The function completed successfully.
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@retval EFI_INVALID_PARAMETER The parameter is NULL.
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**/
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EFI_STATUS
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EFIAPI
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KabylakeRvp3InitPreMem (
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VOID
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)
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{
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PcdSet32S (PcdPcie0WakeGpioNo, 0);
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PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
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PcdSet32S (PcdPcie0HoldRstGpioNo, 8);
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PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);
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PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
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PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);
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PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
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//
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// HSIO PTSS Table
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//
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PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3);
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PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3_Size);
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PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3);
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PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3_Size);
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//
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// DRAM related definition
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//
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PcdSet8S (PcdSaMiscUserBd, 5);
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PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3);
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PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3));
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PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3);
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PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3));
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PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1);
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PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1);
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//
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// Example policy for DIMM slots implementation boards:
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// 1. Assign Smbus address of DIMMs and SpdData will be updated later
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// by reading from DIMM SPD.
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// 2. No need to apply hardcoded SpdData buffers here for such board.
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// Example:
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// PcdMrcSpdAddressTable0 = 0xA0
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// PcdMrcSpdAddressTable1 = 0xA2
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// PcdMrcSpdAddressTable2 = 0xA4
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// PcdMrcSpdAddressTable3 = 0xA6
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// PcdMrcSpdData = 0
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// PcdMrcSpdDataSize = 0
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//
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// Kabylake RVP3 has 8GB Memory down implementation withouit SPD,
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// So assign all SpdAddress to 0 and apply static SpdData buffers:
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// PcdMrcSpdAddressTable0 = 0
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// PcdMrcSpdAddressTable1 = 0
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// PcdMrcSpdAddressTable2 = 0
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// PcdMrcSpdAddressTable3 = 0
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// PcdMrcSpdData = static data buffer
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// PcdMrcSpdDataSize = sizeof (static data buffer)
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//
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PcdSet8S (PcdMrcSpdAddressTable0, 0);
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PcdSet8S (PcdMrcSpdAddressTable1, 0);
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PcdSet8S (PcdMrcSpdAddressTable2, 0);
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PcdSet8S (PcdMrcSpdAddressTable3, 0);
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PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd110);
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PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3Spd110Size);
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PcdSetBoolS (PcdIoExpanderPresent, TRUE);
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return EFI_SUCCESS;
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}
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/**
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SkylaeA0Rvp3 board configuration init function for PEI pre-memory phase.
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PEI_BOARD_CONFIG_PCD_INIT
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@param Content pointer to the buffer contain init information for board init.
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@retval EFI_SUCCESS The function completed successfully.
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@retval EFI_INVALID_PARAMETER The parameter is NULL.
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**/
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EFI_STATUS
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EFIAPI
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SkylakeRvp3InitPreMem (
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VOID
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)
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{
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PcdSet32S (PcdPcie0WakeGpioNo, 0);
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PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
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PcdSet32S (PcdPcie0HoldRstGpioNo, 8);
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PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);
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PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
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PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);
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PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
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//
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// HSIO PTSS Table
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//
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PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3);
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PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_KabylakeRvp3_Size);
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PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3);
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PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_KabylakeRvp3_Size);
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//
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// DRAM related definition
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//
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PcdSet8S (PcdSaMiscUserBd, 5);
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PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3);
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PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3));
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PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3);
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PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3));
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PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1);
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PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1);
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//
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// Example policy for DIMM slots implementation boards:
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// 1. Assign Smbus address of DIMMs and SpdData will be updated later
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// by reading from DIMM SPD.
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// 2. No need to apply hardcoded SpdData buffers here for such board.
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// Example:
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// PcdMrcSpdAddressTable0 = 0xA0
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// PcdMrcSpdAddressTable1 = 0xA2
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// PcdMrcSpdAddressTable2 = 0xA4
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// PcdMrcSpdAddressTable3 = 0xA6
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// PcdMrcSpdData = 0
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// PcdMrcSpdDataSize = 0
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//
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// Skylake RVP3 has 4GB Memory down implementation withouit SPD,
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// So assign all SpdAddress to 0 and apply static SpdData buffers:
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// PcdMrcSpdAddressTable0 = 0
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// PcdMrcSpdAddressTable1 = 0
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// PcdMrcSpdAddressTable2 = 0
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// PcdMrcSpdAddressTable3 = 0
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// PcdMrcSpdData = static data buffer
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// PcdMrcSpdDataSize = sizeof (static data buffer)
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//
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PcdSet8S (PcdMrcSpdAddressTable0, 0);
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PcdSet8S (PcdMrcSpdAddressTable1, 0);
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PcdSet8S (PcdMrcSpdAddressTable2, 0);
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PcdSet8S (PcdMrcSpdAddressTable3, 0);
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PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd);
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PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3SpdSize);
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PcdSetBoolS (PcdIoExpanderPresent, TRUE);
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return EFI_SUCCESS;
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}
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#define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680
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/**
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Configures GPIO.
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@param[in] GpioTable Point to Platform Gpio table
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@param[in] GpioTableCount Number of Gpio table entries
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**/
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VOID
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ConfigureGpio (
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IN GPIO_INIT_CONFIG *GpioDefinition,
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IN UINT16 GpioTableCount
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)
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{
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EFI_STATUS Status;
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DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
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Status = GpioConfigurePads (GpioTableCount, GpioDefinition);
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DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
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}
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/**
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Configure GPIO Before Memory is not ready.
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**/
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VOID
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GpioInitPreMem (
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VOID
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)
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{
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// ConfigureGpio ();
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}
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/**
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Configure Super IO.
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**/
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VOID
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SioInit (
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VOID
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)
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{
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//
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// Program and Enable Default Super IO Configuration Port Addresses and range
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//
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PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10);
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//
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// 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;
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//
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PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10);
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return;
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}
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/**
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Configues the IC2 Controller on which GPIO Expander Communicates.
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This Function is to enable the I2CGPIOExapanderLib to programm the Gpios
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Complete intilization will be done in later Stage
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**/
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VOID
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EFIAPI
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I2CGpioExpanderInitPreMem(
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VOID
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)
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{
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ConfigureSerialIoController (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden);
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SerialIoI2cGpioInit (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden, PchSerialIoIs33V);
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}
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/**
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Configure GPIO and SIO before memory ready.
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@retval EFI_SUCCESS Operation success.
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**/
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EFI_STATUS
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EFIAPI
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KabylakeRvp3BoardInitBeforeMemoryInit (
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VOID
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)
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{
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EFI_STATUS Status;
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if (LibPcdGetSku () == BoardIdKabyLakeYLpddr3Rvp3) {
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KabylakeRvp3InitPreMem ();
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} else if (LibPcdGetSku () == BoardIdSkylakeRvp3) {
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SkylakeRvp3InitPreMem ();
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}
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//
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// Configures the I2CGpioExpander
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//
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if (PcdGetBool (PcdIoExpanderPresent)) {
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I2CGpioExpanderInitPreMem();
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}
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GpioInitPreMem ();
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SioInit ();
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///
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/// Do basic PCH init
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///
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SiliconInit ();
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//
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// Install PCH RESET PPI and EFI RESET2 PeiService
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//
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Status = PchInitializeReset ();
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ASSERT_EFI_ERROR (Status);
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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KabylakeRvp3BoardDebugInit (
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VOID
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)
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{
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///
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/// Do Early PCH init
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///
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EarlySiliconInit ();
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return EFI_SUCCESS;
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}
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EFI_BOOT_MODE
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EFIAPI
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KabylakeRvp3BoardBootModeDetect (
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VOID
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)
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{
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return BOOT_WITH_FULL_CONFIGURATION;
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}
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