/** @file
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ACPI DSDT table
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Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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// Define a Global region of ACPI NVS Region that may be used for any
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// type of implementation. The starting offset and size will be fixed
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// up by the System BIOS during POST. Note that the Size must be a word
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// in size to be fixed up correctly.
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#ifndef _GLOBAL_NVS_AREA_DEF_H_
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#define _GLOBAL_NVS_AREA_DEF_H_
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#pragma pack (push,1)
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typedef struct {
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//
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// Miscellaneous Dynamic Registers:
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//
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UINT16 OperatingSystem; ///< Offset 0 Operating System
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UINT8 SmiFunction; ///< Offset 2 SMI Function Call (ASL to SMI via I/O Trap)
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UINT32 Port80DebugValue; ///< Offset 3 Port 80 Debug Port Value
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UINT8 PowerState; ///< Offset 7 Power State (AC Mode = 1)
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//
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// Thermal Policy Registers:
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//
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UINT8 EnableDigitalThermalSensor; ///< Offset 8 Digital Thermal Sensor Enable
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UINT8 DigitalThermalSensorSmiFunction; ///< Offset 9 DTS SMI Function Call
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//
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// CPU Identification Registers:
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//
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UINT8 ApicEnable; ///< Offset 10 APIC Enabled by SBIOS (APIC Enabled = 1)
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UINT8 ThreadCount; ///< Offset 11 Number of Enabled Threads
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//
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// PCIe Hot Plug
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//
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UINT8 PcieOSCControl; ///< Offset 12 PCIE OSC Control
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UINT8 NativePCIESupport; ///< Offset 13 Native PCIE Setup Value
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//
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// Global Variables
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//
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UINT8 DisplaySupportFlag; ///< Offset 14 _DOS Display Support Flag.
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UINT8 InterruptModeFlag; ///< Offset 15 Global IOAPIC/8259 Interrupt Mode Flag.
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UINT8 L01Counter; ///< Offset 16 Global L01 Counter.
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UINT8 LtrEnable[24]; ///< Offset 17 Latency Tolerance Reporting Enable
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///< Offset 18 Latency Tolerance Reporting Enable
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///< Offset 19 Latency Tolerance Reporting Enable
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///< Offset 20 Latency Tolerance Reporting Enable
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///< Offset 21 Latency Tolerance Reporting Enable
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///< Offset 22 Latency Tolerance Reporting Enable
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///< Offset 23 Latency Tolerance Reporting Enable
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///< Offset 24 Latency Tolerance Reporting Enable
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///< Offset 25 Latency Tolerance Reporting Enable
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///< Offset 26 Latency Tolerance Reporting Enable
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///< Offset 27 Latency Tolerance Reporting Enable
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///< Offset 28 Latency Tolerance Reporting Enable
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///< Offset 29 Latency Tolerance Reporting Enable
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///< Offset 30 Latency Tolerance Reporting Enable
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///< Offset 31 Latency Tolerance Reporting Enable
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///< Offset 32 Latency Tolerance Reporting Enable
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///< Offset 33 Latency Tolerance Reporting Enable
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///< Offset 34 Latency Tolerance Reporting Enable
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///< Offset 35 Latency Tolerance Reporting Enable
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///< Offset 36 Latency Tolerance Reporting Enable
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///< Offset 37 Latency Tolerance Reporting Enable
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///< Offset 38 Latency Tolerance Reporting Enable
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///< Offset 39 Latency Tolerance Reporting Enable
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///< Offset 40 Latency Tolerance Reporting Enable
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UINT8 ObffEnable[24]; ///< Offset 41 Optimized Buffer Flush and Fill
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///< Offset 42 Optimized Buffer Flush and Fill
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///< Offset 43 Optimized Buffer Flush and Fill
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///< Offset 44 Optimized Buffer Flush and Fill
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///< Offset 45 Optimized Buffer Flush and Fill
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///< Offset 46 Optimized Buffer Flush and Fill
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///< Offset 47 Optimized Buffer Flush and Fill
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///< Offset 48 Optimized Buffer Flush and Fill
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///< Offset 49 Optimized Buffer Flush and Fill
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///< Offset 50 Optimized Buffer Flush and Fill
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///< Offset 51 Optimized Buffer Flush and Fill
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///< Offset 52 Optimized Buffer Flush and Fill
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///< Offset 53 Optimized Buffer Flush and Fill
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///< Offset 54 Optimized Buffer Flush and Fill
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///< Offset 55 Optimized Buffer Flush and Fill
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///< Offset 56 Optimized Buffer Flush and Fill
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///< Offset 57 Optimized Buffer Flush and Fill
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///< Offset 58 Optimized Buffer Flush and Fill
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///< Offset 59 Optimized Buffer Flush and Fill
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///< Offset 60 Optimized Buffer Flush and Fill
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///< Offset 61 Optimized Buffer Flush and Fill
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///< Offset 62 Optimized Buffer Flush and Fill
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///< Offset 63 Optimized Buffer Flush and Fill
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///< Offset 64 Optimized Buffer Flush and Fill
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UINT8 Rtd3Support; ///< Offset 65 Runtime D3 support.
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UINT8 LowPowerS0Idle; ///< Offset 66 Low Power S0 Idle Enable
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UINT8 VirtualGpioButtonSxBitmask; ///< Offset 67 Virtual GPIO button Notify Sleep State Change
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UINT8 PstateCapping; ///< Offset 68 P-state Capping
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UINT8 Ps2MouseEnable; ///< Offset 69 Ps2 Mouse Enable
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UINT8 Ps2KbMsEnable; ///< Offset 70 Ps2 Keyboard and Mouse Enable
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//
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// Driver Mode
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//
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UINT32 GpioIrqRoute; ///< Offset 71 GPIO IRQ
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UINT8 PL1LimitCS; ///< Offset 75 set PL1 limit when entering CS
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UINT16 PL1LimitCSValue; ///< Offset 76 PL1 limit value
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UINT8 TenSecondPowerButtonEnable; ///< Offset 78 10sec Power button support
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UINT8 PciDelayOptimizationEcr; ///< Offset 79 Pci Delay Optimization Ecr
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UINT8 TbtSupport; ///< Offset 80 Thunderbolt(TM) support
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UINT8 TbtNativeOsHotPlug; ///< Offset 81 TbtNativeOsHotPlug
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UINT8 TbtSelector; ///< Offset 82 Thunderbolt(TM) Root port selector
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UINT8 TbtSelector1; ///< Offset 83 Thunderbolt(TM) Root port selector
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UINT8 BoardId; ///< Offset 84 Board ID
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} EFI_GLOBAL_NVS_AREA;
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#pragma pack(pop)
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#endif
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