/** @file
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Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiPei.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/PchResetLib.h>
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#include <Library/SiliconInitLib.h>
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#include <Library/TimerLib.h>
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#include <Library/PeiLib.h>
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#include <Library/GpioLib.h>
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#include <GpioPinsSklLp.h>
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#include <IndustryStandard/TpmPtp.h>
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#include <PchAccess.h>
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#include "PeiAspireVn7Dash572GInitLib.h"
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#include <ConfigBlock.h>
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#include <ConfigBlock/MemoryConfig.h>
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#ifndef STALL_ONE_MILLI_SECOND
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#define STALL_ONE_MILLI_SECOND 1000
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#endif
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//
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// Reference RCOMP resistors on motherboard - for Aspire VN7-572G
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//
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GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorAspireVn7Dash572G[SA_MRC_MAX_RCOMP] = { 121, 80, 100 };
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//
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// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for Aspire VN7-572G
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//
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GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetAspireVn7Dash572G[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 };
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//
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// dGPU power GPIO definitions
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#define DGPU_PRESENT GPIO_SKL_LP_GPP_A20 /* Active low */
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#define DGPU_HOLD_RST GPIO_SKL_LP_GPP_B4 /* Active low */
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#define DGPU_PWR_EN GPIO_SKL_LP_GPP_B21 /* Active low */
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EFI_STATUS
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EFIAPI
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AspireVn7Dash572GBoardDetect (
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VOID
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);
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/**
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Aspire VN7-572G board configuration init function for PEI pre-memory phase.
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**/
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VOID
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AspireVn7Dash572GInitPreMem (
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VOID
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)
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{
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//
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// HSIO PTSS Table
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//
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PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_AspireVn7Dash572G);
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PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_AspireVn7Dash572G_Size);
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PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_AspireVn7Dash572G);
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PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_AspireVn7Dash572G_Size);
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//
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// DRAM related definition
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//
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PcdSet8S (PcdSaMiscUserBd, 5); // ULT/ULX/Mobile Halo
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PcdSet8S (PcdMrcCaVrefConfig, 2); // DDR4: "VREF_CA to CH_A and VREF_DQ_B to CH_B"
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// TODO: Clear Dq/Dqs?
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PcdSetBoolS (PcdMrcDqPinsInterleaved, TRUE);
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PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorAspireVn7Dash572G);
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PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetAspireVn7Dash572G);
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//
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// Example policy for DIMM slots implementation boards:
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// 1. Assign Smbus address of DIMMs and SpdData will be updated later
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// by reading from DIMM SPD.
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// 2. No need to apply hardcoded SpdData buffers here for such board.
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// Example:
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// PcdMrcSpdAddressTable0 = 0xA0
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// PcdMrcSpdAddressTable1 = 0xA2
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// PcdMrcSpdAddressTable2 = 0xA4
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// PcdMrcSpdAddressTable3 = 0xA6
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// PcdMrcSpdData = 0
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// PcdMrcSpdDataSize = 0
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//
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PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);
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PcdSet8S (PcdMrcSpdAddressTable1, 0);
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PcdSet8S (PcdMrcSpdAddressTable2, 0xA4);
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PcdSet8S (PcdMrcSpdAddressTable3, 0);
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PcdSet32S (PcdMrcSpdData, 0);
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PcdSet16S (PcdMrcSpdDataSize, 0);
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}
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/**
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Configures GPIO before memory is ready.
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**/
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EFI_STATUS
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EFIAPI
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GpioInitPreMem (
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VOID
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)
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{
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EFI_STATUS Status;
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DEBUG ((DEBUG_INFO, "GpioInitPreMem() Start\n"));
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Status = GpioConfigurePads (mGpioTableAspireVn7Dash572G_earlySize, mGpioTableAspireVn7Dash572G_early);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "Failed to configure early GPIOs!\n"));
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return EFI_DEVICE_ERROR;
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}
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DEBUG ((DEBUG_INFO, "GpioInitPreMem() End\n"));
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return EFI_SUCCESS;
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}
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/**
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Initialises the dGPU.
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**/
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VOID
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DgpuPowerOn (
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VOID
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)
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{
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UINT32 OutputVal;
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DEBUG ((DEBUG_INFO, "DgpuPowerOn() Start\n"));
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GpioGetOutputValue (DGPU_PRESENT, &OutputVal);
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if (!OutputVal) {
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DEBUG ((DEBUG_INFO, "dGPU present, enable power...\n"));
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GpioSetOutputValue (DGPU_HOLD_RST, 0); // Assert dGPU_HOLD_RST#
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MicroSecondDelay (2 * STALL_ONE_MILLI_SECOND);
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GpioSetOutputValue (DGPU_PWR_EN, 0); // Assert dGPU_PWR_EN#
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MicroSecondDelay (7 * STALL_ONE_MILLI_SECOND);
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GpioSetOutputValue (DGPU_HOLD_RST, 1); // Deassert dGPU_HOLD_RST#
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MicroSecondDelay (30 * STALL_ONE_MILLI_SECOND);
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} else {
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DEBUG ((DEBUG_INFO, "dGPU not present, disable power...\n"));
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GpioSetOutputValue (DGPU_HOLD_RST, 0); // Assert dGPU_HOLD_RST#
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GpioSetOutputValue (DGPU_PWR_EN, 1); // Deassert dGPU_PWR_EN#
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}
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DEBUG ((DEBUG_INFO, "DgpuPowerOn() End\n"));
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}
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/**
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Configure LPC.
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**/
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VOID
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LpcInit (
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VOID
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)
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{
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//
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// Program and Enable EC (sideband) Port Addresses and range
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//
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PchLpcGenIoRangeSet (0x68, 0x08);
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//
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// Program and Enable EC (index) Port Addresses and range
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//
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PchLpcGenIoRangeSet (0x1200, 0x10);
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}
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/**
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Configure GPIO and SIO before memory ready.
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@retval EFI_SUCCESS Operation success.
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**/
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EFI_STATUS
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EFIAPI
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AspireVn7Dash572GBoardInitBeforeMemoryInit (
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VOID
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)
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{
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EFI_STATUS Status;
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Status = GpioInitPreMem ();
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if (!EFI_ERROR (Status)) {
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DgpuPowerOn ();
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}
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AspireVn7Dash572GInitPreMem ();
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///
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/// Do basic PCH init
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///
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SiliconInit ();
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//
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// Fix-up LPC configuration
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// Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64h and 62h/66h.
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//
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PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
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PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
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//
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// Install PCH RESET PPI and EFI RESET2 PeiService
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//
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Status = PchInitializeReset ();
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ASSERT_EFI_ERROR (Status);
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return EFI_SUCCESS;
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}
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/**
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Configure GPIO and SIO before memory ready.
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@retval EFI_SUCCESS Operation success.
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**/
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EFI_STATUS
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EFIAPI
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AspireVn7Dash572GBoardInitAfterMemoryInit (
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VOID
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)
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{
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EFI_STATUS Status;
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// BUGBUG: Workaround for a misbehaving system firmware not setting goIdle
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// - Based on prior investigation for coreboot, I suspect FSP
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if ((MmioRead32 (0xFED40044) & PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE) == 0) {
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DEBUG ((DEBUG_WARN, "TPM no-IdleBypass bug: workaround enabled\n"));
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MmioWrite32 (0xFED40040, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);
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}
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// Program the same 64K range of EC memory as vendor FW
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Status = PchLpcMemRangeSet (0xFE800000);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_WARN, "Failed to enable LGMR. Were ACPI tables built for LGMR memory map?\n"));
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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AspireVn7Dash572GBoardDebugInit (
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VOID
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)
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{
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///
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/// Do Early PCH init
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///
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EarlySiliconInit ();
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LpcInit ();
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// NB: MinPlatform specification defines platform initialisation flow.
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// Therefore, we defer board detection until we can program LPC.
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// - Alternatively, move the preceding calls to BoardDetect()
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AspireVn7Dash572GBoardDetect ();
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return EFI_SUCCESS;
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}
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EFI_BOOT_MODE
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EFIAPI
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AspireVn7Dash572GBoardBootModeDetect (
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VOID
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)
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{
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UINT16 ABase;
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UINT32 SleepType;
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DEBUG ((DEBUG_INFO, "Performing boot mode detection\n"));
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// TODO: Perform advanced detection (recovery/capsule)
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// FIXME: This violates PI specification? But BOOT_WITH* would always take precedence
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// over BOOT_ON_S{4,5}...
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PchAcpiBaseGet (&ABase);
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SleepType = IoRead32 (ABase + R_PCH_ACPI_PM1_CNT) & B_PCH_ACPI_PM1_CNT_SLP_TYP;
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switch (SleepType) {
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case V_PCH_ACPI_PM1_CNT_S3:
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return BOOT_ON_S3_RESUME;
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case V_PCH_ACPI_PM1_CNT_S4:
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return BOOT_ON_S4_RESUME;
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// case V_PCH_ACPI_PM1_CNT_S5:
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// return BOOT_ON_S5_RESUME;
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default:
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return BOOT_WITH_FULL_CONFIGURATION;
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}
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}
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