/** @file
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Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiPei.h>
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#include <Library/BoardEcLib.h>
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#include <Library/DebugLib.h>
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#include <Library/EcLib.h>
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#include <Library/GpioLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/PciLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/SiliconInitLib.h>
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#include <PchAccess.h>
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#include <GpioPinsSklLp.h>
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#include "PeiAspireVn7Dash572GInitLib.h"
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/**
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Init from vendor's PeiOemModule. KbcPeim does not appear to be used
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(It implements commands also found in RtKbcDriver and SmmKbcDriver).
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Mostly, this puts the system back to sleep if the lid is closed during
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an S3 resume.
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**/
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VOID
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EcInit (
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VOID
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)
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{
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EFI_BOOT_MODE BootMode;
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UINT8 PowerRegister;
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UINT8 OutData;
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UINT16 ABase;
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UINT16 Pm1Sts;
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UINT32 GpeSts;
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/* This is called via a "$FNC" in a PeiOemModule pointer table, with "$DPX" on SiInit */
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IoWrite8 (0x6C, 0x5A); // 6Ch is the EC sideband port
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PeiServicesGetBootMode (&BootMode);
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if (BootMode == BOOT_ON_S3_RESUME) {
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/* "MLID" in LGMR-based memory map is equivalent to "ELID" in EC-based
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* memory map. Vendor firmware accesses through LGMR; remapped
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* - EcCmd* function calls will not remapped */
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EcRead (0x70, &PowerRegister);
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if (!(PowerRegister & BIT1)) { // Lid is closed
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EcCmd90Read (0x0A, &OutData);
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if (!(OutData & BIT1)) {
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EcCmd91Write (0x0A, OutData | BIT1);
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}
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/* Clear events and go back to sleep */
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PchAcpiBaseGet (&ABase);
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/* Clear ABase PM1_STS - RW/1C set bits */
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Pm1Sts = IoRead16 (ABase + R_PCH_ACPI_PM1_STS);
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IoWrite16 (ABase + R_PCH_ACPI_PM1_STS, Pm1Sts);
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/* Clear ABase GPE0_STS[127:96] - RW/1C set bits */
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GpeSts = IoRead32 (ABase + R_PCH_ACPI_GPE0_STS_127_96);
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IoWrite32 (ABase + R_PCH_ACPI_GPE0_STS_127_96, GpeSts);
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/* Clear xHCI PM_CS[PME_Status] - RW/1C - and disable xHCI PM_CS[PME_En] */
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PciAndThenOr16 (PCI_LIB_ADDRESS(PCI_BUS_NUMBER_PCH_XHCI, PCI_DEVICE_NUMBER_PCH_XHCI, PCI_FUNCTION_NUMBER_PCH_XHCI, R_PCH_XHCI_PWR_CNTL_STS),
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(UINT16) ~B_PCH_XHCI_PWR_CNTL_STS_PME_EN,
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B_PCH_XHCI_PWR_CNTL_STS_PME_STS
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);
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/* Enter S3 sleep */
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IoAndThenOr32 (ABase + R_PCH_ACPI_PM1_CNT,
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(UINT32) ~(B_PCH_ACPI_PM1_CNT_SLP_TYP | B_PCH_ACPI_PM1_CNT_SLP_EN),
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V_PCH_ACPI_PM1_CNT_S3
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);
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IoWrite32 (ABase + R_PCH_ACPI_PM1_CNT, B_PCH_ACPI_PM1_CNT_SLP_EN);
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CpuDeadLoop ();
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}
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}
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}
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/**
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Aspire VN7-572G board configuration init function for PEI post memory phase.
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**/
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VOID
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AspireVn7Dash572GInit (
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VOID
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)
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{
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PcdSet32S (PcdHdaVerbTable, (UINTN) &HdaVerbTableAlc255AspireVn7Dash572G);
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PcdSet32S (PcdDisplayAudioHdaVerbTable, (UINTN) &HdaVerbTableDisplayAudio);
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}
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/**
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Configures GPIO
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**/
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EFI_STATUS
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EFIAPI
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GpioInitPostMem (
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VOID
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)
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{
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EFI_STATUS Status;
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DEBUG ((DEBUG_INFO, "GpioInitPostMem() Start\n"));
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Status = GpioConfigurePads (mGpioTableAspireVn7Dash572GSize, mGpioTableAspireVn7Dash572G);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "Failed to configure early GPIOs!\n"));
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return EFI_DEVICE_ERROR;
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}
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DEBUG ((DEBUG_INFO, "GpioInitPostMem() End\n"));
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return EFI_SUCCESS;
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}
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/**
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Configure GPIO and SIO
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@retval EFI_SUCCESS Operation success.
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**/
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EFI_STATUS
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EFIAPI
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AspireVn7Dash572GBoardInitBeforeSiliconInit (
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VOID
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)
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{
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GpioInitPostMem ();
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AspireVn7Dash572GInit ();
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///
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/// Do Late PCH init
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///
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LateSiliconInit ();
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return EFI_SUCCESS;
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}
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/**
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Notify EC
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@retval EFI_SUCCESS Operation success.
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**/
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EFI_STATUS
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EFIAPI
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AspireVn7Dash572GBoardInitAfterSiliconInit (
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VOID
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)
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{
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EcInit ();
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return EFI_SUCCESS;
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}
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