/** @file
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This file configures Aspire VN7-572G board-specific FSP UPDs.
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Copyright (c) 2021, Baruch Binyamin Doron
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PeiPchPolicyUpdate.h"
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <PchPolicyCommon.h>
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/* TODO:
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* - Validate PCH Sample policies: only SA one used by default.
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* - Remove likely fuse-disabled devices when reset handling is committed?
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* - Remove duplicate policy
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* - Consider updating some policies, rather than overriding. This could be factored into
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* BoardInitLib for deduplication
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* - Copy initialised array, where sane
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* - Set IgdDvmt50PreAlloc? */
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#define SA_VR 0
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#define IA_VR 1
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#define GT_UNSLICED_VR 2
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#define GT_SLICED_VR 3
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// Numbering is one-based indexing. The code uses zero-based indexing,
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// where these are the first unpopulated ports
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#define NUM_POPULATED_USB2_PORTS 9
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#define NUM_POPULATED_USB3_PORTS 4
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// The first three USB2 ports are all also USB3 ports. More specifically,
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// the routing for these is copied from the vendor's SetupUtility
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#define POPULATED_USB3_AS_USB2_PORTS 3
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/**
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Performs the remainder of board-specific FSP Policy initialization.
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@param[in][out] FspmUpd Pointer to FSP UPD Data.
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@retval EFI_SUCCESS FSP UPD Data is updated.
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@retval EFI_NOT_FOUND Fail to locate required PPI.
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@retval Other FSP UPD Data update process fail.
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**/
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EFI_STATUS
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EFIAPI
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PeiFspBoardPolicyUpdatePreMem (
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IN OUT FSPM_UPD *FspmUpd
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)
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{
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DEBUG ((DEBUG_INFO, "%a() Start\n", __FUNCTION__));
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// BUGBUG: Preserve FSP defaults - PeiSiliconPolicyInitLibFsp ultimately overrides to 0.
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// Drop when https://edk2.groups.io/g/devel/message/79391 is merged
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FspmUpd->FspmConfig.PeciC10Reset = 1;
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FspmUpd->FspmConfig.RefClk = 1; // Maybe "auto" is safe, but that isn't the FSP default
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// TODO: Why should this be here?
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FspmUpd->FspmConfig.TsegSize = PcdGet32 (PcdTsegSize);
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/* System Agent config */
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FspmUpd->FspmConfig.UserBd = PcdGet8 (PcdSaMiscUserBd);
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FspmUpd->FspmConfig.DqPinsInterleaved = (UINT8) PcdGetBool (PcdMrcDqPinsInterleaved);
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FspmUpd->FspmConfig.CaVrefConfig = PcdGet8 (PcdMrcCaVrefConfig);
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FspmUpd->FspmConfig.SaGv = 3; // Enabled
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/* iGFX config */
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FspmUpd->FspmConfig.PrimaryDisplay = 4; // Switchable Graphics
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/* PCIe config */
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FspmUpd->FspmConfig.PcieRpEnableMask = 0x341; // Ports 1, 7, 9 and 10
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DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__));
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return EFI_SUCCESS;
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}
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/**
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Performs the remainder of board-specific FSP Policy initialization.
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@param[in][out] FspsUpd Pointer to FSP UPD Data.
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@retval EFI_SUCCESS FSP UPD Data is updated.
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@retval EFI_NOT_FOUND Fail to locate required PPI.
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@retval Other FSP UPD Data update process fail.
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**/
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EFI_STATUS
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EFIAPI
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PeiFspBoardPolicyUpdate (
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IN OUT FSPS_UPD *FspsUpd
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)
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{
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INTN Index;
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DEBUG ((DEBUG_INFO, "%a() Start\n", __FUNCTION__));
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// FIXME/NB: This is insecure and not production-ready!
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// TODO: Configure SPI lockdown by variable on FrontPage?
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// - Later, also configure stronger protection: PRRs
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FspsUpd->FspsConfig.PchLockDownBiosLock = 0; // Default. Will enable, not remove
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FspsUpd->FspsConfig.PchLockDownSpiEiss = 0;
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// This may be PWRM+0x18[BIT22], causing HSTI "PCH Security Configuration - Reserved Check failure"
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// I think the intel_pmc_core kernel module requires this to populate debugfs?
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FspsUpd->FspsTestConfig.PchPmPmcReadDisable = 0;
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// BUGBUG: Preserve FSP defaults - Pei*PolicyLib ultimately overrides
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// Requires HW support?
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FspsUpd->FspsConfig.PchPmSlpS0VmEnable = 0;
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// Do not clear UART2, may be set by PeiPchPolicyUpdate.c:PeiFspPchPolicyUpdate()
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// - Presently always set to PCI by policy
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ZeroMem (&FspsUpd->FspsConfig.SerialIoDevMode, sizeof(FspsUpd->FspsConfig.SerialIoDevMode)-1);
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// I2C controllers are in PCI mode
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// - Board has no GPIO expander on I2C4 (despite SetupUtility claim that it does - this would be static text)
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FspsUpd->FspsConfig.SerialIoDevMode[0] = 2;
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FspsUpd->FspsConfig.SerialIoDevMode[1] = 2;
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// Acer IDs (TODO: "Newgate" IDs)
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FspsUpd->FspsConfig.DefaultSvid = 0x1025;
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FspsUpd->FspsConfig.DefaultSid = 0x1037;
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FspsUpd->FspsConfig.PchSubSystemVendorId = 0x1025;
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FspsUpd->FspsConfig.PchSubSystemId = 0x1037;
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/* System Agent config */
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// Set the Thermal Control Circuit (TCC) activation value to 97C
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// even though FSP integration guide says to set it to 100C for SKL-U
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// (offset at 0), because when the TCC activates at 100C, the CPU
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// will have already shut itself down from overheating protection.
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FspsUpd->FspsTestConfig.TccActivationOffset = 3;
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// VR Slew rate setting for improving audible noise
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FspsUpd->FspsConfig.AcousticNoiseMitigation = 1;
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FspsUpd->FspsConfig.SlowSlewRateForIa = 3; // Fast/16
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FspsUpd->FspsConfig.SlowSlewRateForGt = 3; // Fast/16
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FspsUpd->FspsConfig.SlowSlewRateForSa = 0; // Fast/2
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FspsUpd->FspsConfig.FastPkgCRampDisableIa = 0;
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FspsUpd->FspsConfig.FastPkgCRampDisableGt = 0;
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FspsUpd->FspsConfig.FastPkgCRampDisableSa = 0;
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// VR domain configuration (copied from board port, before VR config moved
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// to SoC. Should match SKL-U (GT2, 15W) in the SKL-U datasheet, vol. 1)
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FspsUpd->FspsConfig.AcLoadline[SA_VR] = 1030; // 10.3mOhm (in 1/100 increments)
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FspsUpd->FspsConfig.DcLoadline[SA_VR] = 1030; // 10.3mOhm (in 1/100 increments)
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FspsUpd->FspsConfig.Psi1Threshold[SA_VR] = 80; // 20A (in 1/4 increments)
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FspsUpd->FspsConfig.Psi2Threshold[SA_VR] = 16; // 4A (in 1/4 increments)
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FspsUpd->FspsConfig.Psi3Threshold[SA_VR] = 4; // 1A (in 1/4 increments)
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FspsUpd->FspsConfig.IccMax[SA_VR] = 18; // 4.5A (in 1/4 increments)
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FspsUpd->FspsConfig.VrVoltageLimit[SA_VR] = 1520; // 1520mV
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FspsUpd->FspsConfig.AcLoadline[IA_VR] = 240; // 2.4mOhm (in 1/100 increments)
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FspsUpd->FspsConfig.DcLoadline[IA_VR] = 240; // 2.4mOhm (in 1/100 increments)
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FspsUpd->FspsConfig.Psi1Threshold[IA_VR] = 80; // 20A (in 1/4 increments)
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FspsUpd->FspsConfig.Psi2Threshold[IA_VR] = 20; // 5A (in 1/4 increments)
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FspsUpd->FspsConfig.Psi3Threshold[IA_VR] = 4; // 1A (in 1/4 increments)
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FspsUpd->FspsConfig.IccMax[IA_VR] = 116; // 29A (in 1/4 increments)
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FspsUpd->FspsConfig.VrVoltageLimit[IA_VR] = 1520; // 1520mV
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FspsUpd->FspsConfig.AcLoadline[GT_UNSLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
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FspsUpd->FspsConfig.DcLoadline[GT_UNSLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
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FspsUpd->FspsConfig.Psi1Threshold[GT_UNSLICED_VR] = 80; // 20A (in 1/4 increments)
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FspsUpd->FspsConfig.Psi2Threshold[GT_UNSLICED_VR] = 20; // 5A (in 1/4 increments)
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FspsUpd->FspsConfig.Psi3Threshold[GT_UNSLICED_VR] = 4; // 1A (in 1/4 increments)
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FspsUpd->FspsConfig.IccMax[GT_UNSLICED_VR] = 124; // 31A (in 1/4 increments)
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FspsUpd->FspsConfig.VrVoltageLimit[GT_UNSLICED_VR] = 1520; // 1520mV
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FspsUpd->FspsConfig.AcLoadline[GT_SLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
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FspsUpd->FspsConfig.DcLoadline[GT_SLICED_VR] = 310; // 3.1mOhm (in 1/100 increments)
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FspsUpd->FspsConfig.Psi1Threshold[GT_SLICED_VR] = 80; // 20A (in 1/4 increments)
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FspsUpd->FspsConfig.Psi2Threshold[GT_SLICED_VR] = 20; // 5A (in 1/4 increments)
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FspsUpd->FspsConfig.Psi3Threshold[GT_SLICED_VR] = 4; // 1A (in 1/4 increments)
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FspsUpd->FspsConfig.IccMax[GT_SLICED_VR] = 124; // 31A (in 1/4 increments)
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FspsUpd->FspsConfig.VrVoltageLimit[GT_SLICED_VR] = 1520; // 1520mV
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// PL1, PL2 override 35W, PL4 override 43W (converted to processor units, then 125 mW increments)
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// BUGBUG: PL1 and PL2 not being configured in MSR 0x610. Requires additional UPD?
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FspsUpd->FspsTestConfig.PowerLimit1 = 35000;
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FspsUpd->FspsTestConfig.PowerLimit2Power = 35000;
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FspsUpd->FspsTestConfig.PowerLimit4 = 43000;
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// ISL95857 VR
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// Send VR specific command for PS4 exit issue
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FspsUpd->FspsConfig.SendVrMbxCmd1 = 2;
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// Send VR mailbox command for IA/GT/SA rails
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FspsUpd->FspsConfig.IslVrCmd = 2;
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/* Skycam config */
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FspsUpd->FspsConfig.SaImguEnable = 0;
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FspsUpd->FspsConfig.PchCio2Enable = 0;
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/* Sensor hub config */
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FspsUpd->FspsConfig.PchIshEnable = 0;
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/* xHCI config */
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FspsUpd->FspsConfig.SsicPortEnable = 0;
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// Configure USB2 ports in two sets
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for (Index = 0; Index < POPULATED_USB3_AS_USB2_PORTS; Index++) {
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FspsUpd->FspsConfig.Usb2AfeTxiset[Index] = 0x2; // 16.9mV
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FspsUpd->FspsConfig.Usb2AfePredeemp[Index] = 1; // De-emphasis on
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FspsUpd->FspsConfig.Usb2AfePetxiset[Index] = 0x3; // 28.15mV
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FspsUpd->FspsConfig.Usb2AfePehalfbit[Index] = 1; // Half-bit
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FspsUpd->FspsConfig.Usb2OverCurrentPin[Index] = PchUsbOverCurrentPinSkip;
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}
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for (Index = POPULATED_USB3_AS_USB2_PORTS; Index < NUM_POPULATED_USB2_PORTS; Index++) {
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FspsUpd->FspsConfig.Usb2AfeTxiset[Index] = 0; // 0mV
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FspsUpd->FspsConfig.Usb2AfePredeemp[Index] = 0x2; // Pre-emphasis and de-emphasis on
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FspsUpd->FspsConfig.Usb2AfePetxiset[Index] = 0x7; // 56.3mV
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FspsUpd->FspsConfig.Usb2AfePehalfbit[Index] = 1; // Half-bit
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FspsUpd->FspsConfig.Usb2OverCurrentPin[Index] = PchUsbOverCurrentPinSkip;
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}
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// Configure all USB3 ports
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for (Index = 0; Index < NUM_POPULATED_USB3_PORTS; Index++) {
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FspsUpd->FspsConfig.Usb3HsioTxDeEmphEnable[Index] = 1;
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FspsUpd->FspsConfig.Usb3HsioTxDeEmph[Index] = 0x29; // Default (approximately -3.5dB de-emphasis)
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FspsUpd->FspsConfig.Usb3OverCurrentPin[Index] = PchUsbOverCurrentPinSkip;
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}
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// Disable supported, but not present, ports
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for (Index = NUM_POPULATED_USB2_PORTS; Index < PCH_LP_XHCI_MAX_USB2_PORTS; Index++) {
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FspsUpd->FspsConfig.PortUsb20Enable[Index] = 0;
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}
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for (Index = NUM_POPULATED_USB3_PORTS; Index < PCH_LP_XHCI_MAX_USB3_PORTS; Index++) {
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FspsUpd->FspsConfig.PortUsb30Enable[Index] = 0;
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}
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/* xDCI config */
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FspsUpd->FspsConfig.XdciEnable = 0;
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/* SATA config */
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// This is a hard silicon requirement, discovered several times by coreboot boards
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FspsUpd->FspsConfig.SataPwrOptEnable = 1;
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// Disable supported, but not present, ports
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FspsUpd->FspsConfig.SataPortsEnable[0] = 0;
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/* PCIe config */
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// Port 1 (dGPU; x4)
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FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[0] = 1;
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FspsUpd->FspsConfig.PcieRpLtrEnable[0] = 1;
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FspsUpd->FspsConfig.PcieRpClkReqSupport[0] = 1;
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FspsUpd->FspsConfig.PcieRpClkReqNumber[0] = 0;
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FspsUpd->FspsConfig.PcieRpMaxPayload[0] = PchPcieMaxPayload256;
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FspsUpd->FspsConfig.PcieRpClkSrcNumber[0] = 0x1F; // CLKSRC pin invalid
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// Port 7 (NGFF; x2)
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FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[6] = 1;
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FspsUpd->FspsConfig.PcieRpLtrEnable[6] = 1;
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FspsUpd->FspsConfig.PcieRpClkReqSupport[6] = 1;
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FspsUpd->FspsConfig.PcieRpClkReqNumber[6] = 3;
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FspsUpd->FspsConfig.PcieRpMaxPayload[6] = PchPcieMaxPayload256;
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FspsUpd->FspsConfig.PcieRpClkSrcNumber[6] = 0x1F; // CLKSRC pin invalid
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// Port 9 (LAN)
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FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[8] = 1;
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FspsUpd->FspsConfig.PcieRpLtrEnable[8] = 1;
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FspsUpd->FspsConfig.PcieRpClkReqSupport[8] = 1;
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FspsUpd->FspsConfig.PcieRpClkReqNumber[8] = 1;
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FspsUpd->FspsConfig.PcieRpMaxPayload[8] = PchPcieMaxPayload256;
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FspsUpd->FspsConfig.PcieRpClkSrcNumber[8] = 0x1F; // CLKSRC pin invalid
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// Port 10 (WLAN)
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FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[9] = 1;
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FspsUpd->FspsConfig.PcieRpLtrEnable[9] = 1;
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FspsUpd->FspsConfig.PcieRpClkReqSupport[9] = 1;
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FspsUpd->FspsConfig.PcieRpClkReqNumber[9] = 2;
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FspsUpd->FspsConfig.PcieRpMaxPayload[9] = PchPcieMaxPayload256;
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FspsUpd->FspsConfig.PcieRpClkSrcNumber[9] = 0x1F; // CLKSRC pin invalid
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// ASPM L0s is broken/unsupported on Qualcomm Atheros QCA6174 (AER: corrected errors)
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// BUGBUG: PcieDeviceTable.c entries aren't setting PCI config space
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FspsUpd->FspsConfig.PcieRpAspm[9] = PchPcieAspmL1;
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/* SCS config */
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// Although platform NVS area shows this enabled, the SD card reader is connected over USB, not SCS
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FspsUpd->FspsConfig.ScsEmmcEnabled = 0;
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FspsUpd->FspsConfig.ScsSdCardEnabled = 0;
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/* LPC config */
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// EC/KBC requires continuous mode
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FspsUpd->FspsConfig.PchPmLpcClockRun = 1;
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FspsUpd->FspsConfig.PchSirqMode = PchContinuousMode;
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/* HDA config */
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// FIXME: DspEnable is set, per PeiPchPolicyLib, however it is disabled in the HOB produced by FSP
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// Returned to DXE as HOB, used to select blob for NHLT
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// - FIXME: 1ch array DMIC may not be supported by the Linux driver
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FspsUpd->FspsConfig.PchHdaDspEndpointDmic = PchHdaDmic1chArray;
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/* GbE config */
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FspsUpd->FspsConfig.PchLanEnable = 0;
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DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__));
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return EFI_SUCCESS;
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}
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