/** @file
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Platform Stage System Agent initialization.
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PeiSaPolicyUpdate.h"
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#include <CpuRegs.h>
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#include <Register/Cpuid.h>
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#include <Library/CpuPlatformLib.h>
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#include <Guid/MemoryTypeInformation.h>
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#include <Guid/MemoryOverwriteControl.h>
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#include <Library/HobLib.h>
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#include <Platform.h>
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#include <PlatformBoardConfig.h>
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#include <Library/SiPolicyLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PeiSaPolicyLib.h>
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#include <Library/GpioLib.h>
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#include <Library/ConfigBlockLib.h>
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///
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/// Memory Reserved should be between 125% to 150% of the Current required memory
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/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resume issues.
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///
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GLOBAL_REMOVE_IF_UNREFERENCED STATIC EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
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{ EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemorySize) }, // ASL
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{ EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize) }, // ACPI NVS (including S3 related)
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{ EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySize) }, // BIOS Reserved (including S3 related)
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{ EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize) }, // Runtime Service Data
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{ EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize) }, // Runtime Service Code
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{ EfiMaxMemoryType, 0 }
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};
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/**
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UpdatePeiSaPolicyPreMem performs SA PEI Policy initialization
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@param[in out] SiPreMemPolicyPpi - SI_PREMEM_POLICY PPI
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@retval EFI_SUCCESS The policy is installed and initialized.
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**/
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EFI_STATUS
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UpdatePeiSaPolicyPreMem (
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IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
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)
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{
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EFI_STATUS Status;
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SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig = NULL;
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MEMORY_CONFIG_NO_CRC *MemConfigNoCrc = NULL;
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SA_MEMORY_RCOMP *RcompData;
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WDT_PPI *gWdtPei;
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UINT8 Index;
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UINTN DataSize;
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EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1];
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EFI_BOOT_MODE BootMode;
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UINT32 TraceHubTotalMemSize;
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GRAPHICS_PEI_PREMEM_CONFIG *GtPreMemConfig = NULL;
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MEMORY_CONFIGURATION *MemConfig = NULL;
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PCIE_PEI_PREMEM_CONFIG *PciePeiPreMemConfig = NULL;
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SWITCHABLE_GRAPHICS_CONFIG *SgGpioData = NULL;
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IPU_PREMEM_CONFIG *IpuPreMemPolicy = NULL;
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OVERCLOCKING_PREMEM_CONFIG *OcPreMemConfig = NULL;
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VTD_CONFIG *Vtd = NULL;
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UINT32 ProcessorTraceTotalMemSize;
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TraceHubTotalMemSize = 0;
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ProcessorTraceTotalMemSize = 0;
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DEBUG((DEBUG_INFO, "Entering Get Config Block function call from UpdatePeiSaPolicyPreMem\n"));
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Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
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ASSERT_EFI_ERROR(Status);
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Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gGraphicsPeiPreMemConfigGuid, (VOID *) &GtPreMemConfig);
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ASSERT_EFI_ERROR(Status);
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Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid, (VOID *) &MemConfig);
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ASSERT_EFI_ERROR(Status);
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Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaPciePeiPreMemConfigGuid, (VOID *) &PciePeiPreMemConfig);
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ASSERT_EFI_ERROR(Status);
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Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSwitchableGraphicsConfigGuid, (VOID *) &SgGpioData);
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ASSERT_EFI_ERROR(Status);
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Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gIpuPreMemConfigGuid, (VOID *) &IpuPreMemPolicy);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
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ASSERT_EFI_ERROR(Status);
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Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaOverclockingPreMemConfigGuid, (VOID *) &OcPreMemConfig);
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ASSERT_EFI_ERROR(Status);
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Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gVtdConfigGuid, (VOID *)&Vtd);
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ASSERT_EFI_ERROR(Status);
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RcompData = MemConfigNoCrc->RcompData;
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//
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// Locate WDT_PPI (ICC WDT PPI)
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//
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gWdtPei = NULL;
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Status = PeiServicesLocatePpi(
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&gWdtPpiGuid,
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0,
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NULL,
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(VOID **) &gWdtPei
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);
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Status = PeiServicesGetBootMode(&BootMode);
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ASSERT_EFI_ERROR(Status);
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MiscPeiPreMemConfig->S3DataPtr = NULL;
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MiscPeiPreMemConfig->UserBd = 0; // It's a CRB mobile board by default (btCRBMB)
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PcdSetBoolS (PcdMobileDramPresent, (BOOLEAN) (MemConfig->MobilePlatform));
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MiscPeiPreMemConfig->SpdAddressTable[0] = PcdGet8 (PcdMrcSpdAddressTable0);
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MiscPeiPreMemConfig->SpdAddressTable[1] = PcdGet8 (PcdMrcSpdAddressTable1);
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MiscPeiPreMemConfig->SpdAddressTable[2] = PcdGet8 (PcdMrcSpdAddressTable2);
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MiscPeiPreMemConfig->SpdAddressTable[3] = PcdGet8 (PcdMrcSpdAddressTable3);
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MemConfig->CaVrefConfig = PcdGet8 (PcdMrcCaVrefConfig);
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MemConfig->DualDimmPerChannelBoardType = PcdGetBool (PcdDualDimmPerChannelBoardType);
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if (PcdGet32 (PcdMrcRcompResistor)) {
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CopyMem((VOID *)RcompData->RcompResistor, (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor), sizeof (RcompData->RcompResistor));
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}
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if (PcdGet32 (PcdMrcRcompTarget)) {
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CopyMem((VOID *)RcompData->RcompTarget, (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget), sizeof (RcompData->RcompTarget));
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}
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if (PcdGet32 (PcdMrcDqByteMap)) {
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CopyMem((VOID *)MemConfigNoCrc->DqByteMap, (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap), sizeof (UINT8)* SA_MC_MAX_CHANNELS * SA_MRC_ITERATION_MAX * 2);
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}
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if (PcdGet32 (PcdMrcDqsMapCpu2Dram)) {
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CopyMem((VOID *)MemConfigNoCrc->DqsMap, (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram), sizeof (UINT8)* SA_MC_MAX_CHANNELS * SA_MC_MAX_BYTES_NO_ECC);
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}
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if (PcdGetBool (PcdMrcDqPinsInterleavedControl)) {
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MemConfig->DqPinsInterleaved = PcdGetBool (PcdMrcDqPinsInterleaved);
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}
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if (PcdGet32 (PcdMrcSpdData)) {
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CopyMem((VOID *)MemConfigNoCrc->SpdData->SpdData[0][0], (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
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CopyMem((VOID *)MemConfigNoCrc->SpdData->SpdData[1][0], (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
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}
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MiscPeiPreMemConfig->MchBar = (UINTN) PcdGet64 (PcdMchBaseAddress);
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MiscPeiPreMemConfig->DmiBar = (UINTN) PcdGet64 (PcdDmiBaseAddress);
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MiscPeiPreMemConfig->EpBar = (UINTN) PcdGet64 (PcdEpBaseAddress);
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MiscPeiPreMemConfig->EdramBar = (UINTN) PcdGet64 (PcdEdramBaseAddress);
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MiscPeiPreMemConfig->SmbusBar = PcdGet16(PcdSmbusBaseAddress);
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MiscPeiPreMemConfig->TsegSize = PcdGet32(PcdTsegSize);
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MiscPeiPreMemConfig->UserBd = PcdGet8 (PcdSaMiscUserBd);
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MiscPeiPreMemConfig->MmioSizeAdjustment = PcdGet16 (PcdSaMiscMmioSizeAdjustment);
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if (PcdGetBool (PcdPegGpioResetControl)) {
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PciePeiPreMemConfig->PegGpioData.GpioSupport = PcdGetBool (PcdPegGpioResetSupoort);
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} else {
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}
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PciePeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.GpioPad = PcdGet32 (PcdPeg0ResetGpioPad);
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PciePeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.Active = PcdGetBool (PcdPeg0ResetGpioActive);
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PciePeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.GpioPad = PcdGet32 (PcdPeg3ResetGpioPad);
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PciePeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.Active = PcdGetBool (PcdPeg3ResetGpioActive);
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MemConfig->CkeRankMapping = 0xAA;
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///
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/// Initialize the VTD Configuration
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///
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Vtd->VtdDisable = 0;
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MemConfig->RMT = 1;
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MemConfig->UserPowerWeightsEn = 0;
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MemConfig->RaplLim2WindY = 0x0A;
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MemConfig->ExitOnFailure = 1;
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MemConfigNoCrc->PlatformMemorySize = PEI_MIN_MEMORY_SIZE + TraceHubTotalMemSize + ProcessorTraceTotalMemSize;
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DataSize = sizeof (mDefaultMemoryTypeInformation);
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CopyMem(MemoryData, mDefaultMemoryTypeInformation, DataSize);
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if (BootMode != BOOT_IN_RECOVERY_MODE) {
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for (Index = 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATION); Index++) {
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MemConfigNoCrc->PlatformMemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE;
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}
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OcPreMemConfig->GtMaxOcRatio = 0;
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OcPreMemConfig->GtVoltageMode = 0;
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OcPreMemConfig->GtVoltageOverride = 0;
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OcPreMemConfig->GtExtraTurboVoltage = 0;
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OcPreMemConfig->GtVoltageOffset = 0;
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OcPreMemConfig->SaVoltageOffset = 0;
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OcPreMemConfig->GtusMaxOcRatio = 0;
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OcPreMemConfig->GtusVoltageMode = 0;
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OcPreMemConfig->GtusVoltageOverride = 0;
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OcPreMemConfig->GtusExtraTurboVoltage = 0;
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OcPreMemConfig->GtusVoltageOffset = 0;
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///
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/// Build the GUID'd HOB for DXE
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///
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BuildGuidDataHob (
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&gEfiMemoryTypeInformationGuid,
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MemoryData,
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DataSize
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);
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}
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return EFI_SUCCESS;
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}
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