/** @file
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This file is SampleCode of the library for Intel PCH PEI Policy initialization.
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PeiPchPolicyUpdate.h"
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#include <Library/BaseMemoryLib.h>
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#include <Library/HdaVerbTableLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/HobLib.h>
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#include <Library/PchGbeLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/SataLib.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchSerialIoLib.h>
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#include <Library/PchPcieRpLib.h>
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#include <Ppi/Spi.h>
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#include <GpioConfig.h>
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#include <Library/DebugLib.h>
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#include <Library/PchGbeLib.h>
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#include <PlatformBoardConfig.h>
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#include <Library/CnviLib.h>
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#include <Register/PchRegsLpcCnl.h>
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#include <PcieDeviceOverrideTable.h>
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#include <Library/ConfigBlockLib.h>
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VOID
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UpdatePcieClockInfo (
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PCH_PCIE_CONFIG *PcieRpConfig,
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UINTN Index,
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UINT64 Data
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)
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{
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PCD64_BLOB Pcd64;
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Pcd64.Blob = Data;
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DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, Supported %x\n", Index, Pcd64.PcieClock.ClockUsage, Pcd64.PcieClock.ClkReqSupported));
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PcieRpConfig->PcieClock[Index].Usage = (UINT8)Pcd64.PcieClock.ClockUsage;
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if (Pcd64.PcieClock.ClkReqSupported) {
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PcieRpConfig->PcieClock[Index].ClkReq = (UINT8)Index;
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} else {
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PcieRpConfig->PcieClock[Index].ClkReq = 0xFF;
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}
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}
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/**
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This is helper function for getting I2C Pads Internal Termination settings from Pcd
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@param[in] Index I2C Controller Index
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**/
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UINT8
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GetSerialIoI2cPadsTerminationFromPcd (
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IN UINT8 Index
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)
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{
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switch (Index) {
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case 0:
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return PcdGet8 (PcdPchSerialIoI2c0PadInternalTerm);
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case 1:
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return PcdGet8 (PcdPchSerialIoI2c1PadInternalTerm);
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case 2:
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return PcdGet8 (PcdPchSerialIoI2c2PadInternalTerm);
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case 3:
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return PcdGet8 (PcdPchSerialIoI2c3PadInternalTerm);
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case 4:
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return PcdGet8 (PcdPchSerialIoI2c4PadInternalTerm);
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case 5:
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return PcdGet8 (PcdPchSerialIoI2c5PadInternalTerm);
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default:
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ASSERT (FALSE); // Invalid I2C Controller Index
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}
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return 0;
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}
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/**
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This is a helper function for updating USB Policy according to Blob data
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@param[in] UsbConfig Pointer to USB_CONFIG data buffer
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@param[in] PortIndex USB Port index
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@param[in] Data32 Blob containing USB2 Afe (PCD32_BLOB) data
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**/
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VOID
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UpdateUsb20AfePolicy (
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IN USB_CONFIG *UsbConfig,
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IN UINT8 PortIndex,
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UINT32 Data32
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)
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{
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PCD32_BLOB Pcd32;
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Pcd32.Blob = Data32;
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if (PortIndex < MAX_USB2_PORTS && Pcd32.Info.Petxiset != 0) {
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UsbConfig->PortUsb20[PortIndex].Afe.Petxiset = Pcd32.Info.Petxiset;
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UsbConfig->PortUsb20[PortIndex].Afe.Txiset = Pcd32.Info.Txiset;
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UsbConfig->PortUsb20[PortIndex].Afe.Predeemp = Pcd32.Info.Predeemp;
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UsbConfig->PortUsb20[PortIndex].Afe.Pehalfbit = Pcd32.Info.Pehalfbit;
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}
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}
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/**
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This function updates USB Policy per port OC Pin number
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@param[in] PchUsbConfig Pointer to USB_CONFIG data buffer
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@param[in] PortIndex USB Port index
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@param[in] Pin OverCurrent pin number
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**/
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VOID
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UpdateUsb20OverCurrentPolicy (
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IN USB_CONFIG *UsbConfig,
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IN UINT8 PortIndex,
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UINT8 Pin
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)
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{
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if (PortIndex < MAX_USB2_PORTS && ((Pin < UsbOverCurrentPinMax) || (Pin == UsbOverCurrentPinSkip))) {
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UsbConfig->PortUsb20[PortIndex].OverCurrentPin = Pin;
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} else {
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if (PortIndex >= MAX_USB2_PORTS) {
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DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: USB2 port number %d is not a valid USB2 port number\n", PortIndex));
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} else {
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DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: Invalid OverCurrent pin specified USB2 port %d\n", PortIndex));
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}
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}
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}
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/**
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This function updates USB Policy per port OC Pin number
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@param[in] PchUsbConfig Pointer to USB_CONFIG data buffer
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@param[in] PortIndex USB Port index
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@param[in] Pin OverCurrent pin number
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**/
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VOID
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UpdateUsb30OverCurrentPolicy (
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IN USB_CONFIG *UsbConfig,
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IN UINT8 PortIndex,
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UINT8 Pin
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)
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{
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if (PortIndex < MAX_USB3_PORTS && ((Pin < UsbOverCurrentPinMax) || (Pin == UsbOverCurrentPinSkip))) {
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UsbConfig->PortUsb30[PortIndex].OverCurrentPin = Pin;
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} else {
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if (PortIndex >= MAX_USB2_PORTS) {
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DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: USB3 port number %d is not a valid USB3 port number\n", PortIndex));
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} else {
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DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: Invalid OverCurrent pin specified USB3 port %d\n", PortIndex));
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}
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}
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}
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/**
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This function performs PCH USB Platform Policy initialization
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@param[in] PchUsbConfig Pointer to USB_CONFIG data buffer
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@param[in] PchSetup Pointer to PCH_SETUP data buffer
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**/
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VOID
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UpdatePchUsbConfig (
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IN USB_CONFIG *UsbConfig
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)
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{
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UINTN PortIndex;
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UsbConfig->OverCurrentEnable = TRUE;
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for (PortIndex = 0; PortIndex < GetPchUsb2MaxPhysicalPortNum (); PortIndex++) {
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UsbConfig->PortUsb20[PortIndex].Enable = TRUE;
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}
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for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) {
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UsbConfig->PortUsb30[PortIndex].Enable = TRUE;
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}
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UsbConfig->XdciConfig.Enable = FALSE;
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//
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// USB2 AFE settings.
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//
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UpdateUsb20AfePolicy (UsbConfig, 0, PcdGet32 (PcdUsb20Port0Afe));
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UpdateUsb20AfePolicy (UsbConfig, 1, PcdGet32 (PcdUsb20Port1Afe));
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UpdateUsb20AfePolicy (UsbConfig, 2, PcdGet32 (PcdUsb20Port2Afe));
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UpdateUsb20AfePolicy (UsbConfig, 3, PcdGet32 (PcdUsb20Port3Afe));
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UpdateUsb20AfePolicy (UsbConfig, 4, PcdGet32 (PcdUsb20Port4Afe));
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UpdateUsb20AfePolicy (UsbConfig, 5, PcdGet32 (PcdUsb20Port5Afe));
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UpdateUsb20AfePolicy (UsbConfig, 6, PcdGet32 (PcdUsb20Port6Afe));
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UpdateUsb20AfePolicy (UsbConfig, 7, PcdGet32 (PcdUsb20Port7Afe));
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UpdateUsb20AfePolicy (UsbConfig, 8, PcdGet32 (PcdUsb20Port8Afe));
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UpdateUsb20AfePolicy (UsbConfig, 9, PcdGet32 (PcdUsb20Port9Afe));
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UpdateUsb20AfePolicy (UsbConfig,10, PcdGet32 (PcdUsb20Port10Afe));
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UpdateUsb20AfePolicy (UsbConfig,11, PcdGet32 (PcdUsb20Port11Afe));
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UpdateUsb20AfePolicy (UsbConfig,12, PcdGet32 (PcdUsb20Port12Afe));
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UpdateUsb20AfePolicy (UsbConfig,13, PcdGet32 (PcdUsb20Port13Afe));
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UpdateUsb20AfePolicy (UsbConfig,14, PcdGet32 (PcdUsb20Port14Afe));
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UpdateUsb20AfePolicy (UsbConfig,15, PcdGet32 (PcdUsb20Port15Afe));
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//
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// Platform Board programming per the layout of each port.
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//
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UpdateUsb20OverCurrentPolicy (UsbConfig, 0, PcdGet8 (PcdUsb20OverCurrentPinPort0));
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UpdateUsb20OverCurrentPolicy (UsbConfig, 1, PcdGet8 (PcdUsb20OverCurrentPinPort1));
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UpdateUsb20OverCurrentPolicy (UsbConfig, 2, PcdGet8 (PcdUsb20OverCurrentPinPort2));
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UpdateUsb20OverCurrentPolicy (UsbConfig, 3, PcdGet8 (PcdUsb20OverCurrentPinPort3));
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UpdateUsb20OverCurrentPolicy (UsbConfig, 4, PcdGet8 (PcdUsb20OverCurrentPinPort4));
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UpdateUsb20OverCurrentPolicy (UsbConfig, 5, PcdGet8 (PcdUsb20OverCurrentPinPort5));
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UpdateUsb20OverCurrentPolicy (UsbConfig, 6, PcdGet8 (PcdUsb20OverCurrentPinPort6));
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UpdateUsb20OverCurrentPolicy (UsbConfig, 7, PcdGet8 (PcdUsb20OverCurrentPinPort7));
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UpdateUsb20OverCurrentPolicy (UsbConfig, 8, PcdGet8 (PcdUsb20OverCurrentPinPort8));
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UpdateUsb20OverCurrentPolicy (UsbConfig, 9, PcdGet8 (PcdUsb20OverCurrentPinPort9));
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UpdateUsb20OverCurrentPolicy (UsbConfig,10, PcdGet8 (PcdUsb20OverCurrentPinPort10));
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UpdateUsb20OverCurrentPolicy (UsbConfig,11, PcdGet8 (PcdUsb20OverCurrentPinPort11));
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UpdateUsb20OverCurrentPolicy (UsbConfig,12, PcdGet8 (PcdUsb20OverCurrentPinPort12));
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UpdateUsb20OverCurrentPolicy (UsbConfig,13, PcdGet8 (PcdUsb20OverCurrentPinPort13));
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UpdateUsb20OverCurrentPolicy (UsbConfig,14, PcdGet8 (PcdUsb20OverCurrentPinPort14));
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UpdateUsb20OverCurrentPolicy (UsbConfig,15, PcdGet8 (PcdUsb20OverCurrentPinPort15));
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UpdateUsb30OverCurrentPolicy (UsbConfig, 0, PcdGet8 (PcdUsb30OverCurrentPinPort0));
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UpdateUsb30OverCurrentPolicy (UsbConfig, 1, PcdGet8 (PcdUsb30OverCurrentPinPort1));
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UpdateUsb30OverCurrentPolicy (UsbConfig, 2, PcdGet8 (PcdUsb30OverCurrentPinPort2));
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UpdateUsb30OverCurrentPolicy (UsbConfig, 3, PcdGet8 (PcdUsb30OverCurrentPinPort3));
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UpdateUsb30OverCurrentPolicy (UsbConfig, 4, PcdGet8 (PcdUsb30OverCurrentPinPort4));
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UpdateUsb30OverCurrentPolicy (UsbConfig, 5, PcdGet8 (PcdUsb30OverCurrentPinPort5));
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UpdateUsb30OverCurrentPolicy (UsbConfig, 6, PcdGet8 (PcdUsb30OverCurrentPinPort6));
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UpdateUsb30OverCurrentPolicy (UsbConfig, 7, PcdGet8 (PcdUsb30OverCurrentPinPort7));
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UpdateUsb30OverCurrentPolicy (UsbConfig, 8, PcdGet8 (PcdUsb30OverCurrentPinPort8));
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UpdateUsb30OverCurrentPolicy (UsbConfig, 9, PcdGet8 (PcdUsb30OverCurrentPinPort9));
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}
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/**
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Return if input ImageGuid belongs to system FMP GUID list.
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@param[in] ImageGuid A pointer to GUID
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@retval TRUE ImageGuid is in the list of PcdSystemFmpCapsuleImageTypeIdGuid
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@retval FALSE ImageGuid is not in the list of PcdSystemFmpCapsuleImageTypeIdGuid
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**/
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BOOLEAN
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IsSystemFmpGuid (
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IN GUID *ImageGuid
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)
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{
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GUID *Guid;
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UINTN Count;
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UINTN Index;
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Guid = PcdGetPtr (PcdSystemFmpCapsuleImageTypeIdGuid);
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Count = PcdGetSize (PcdSystemFmpCapsuleImageTypeIdGuid) / sizeof (GUID);
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for (Index = 0; Index < Count; Index++, Guid++) {
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if (CompareGuid (ImageGuid, Guid)) {
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return TRUE;
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}
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}
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return FALSE;
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}
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/**
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This function performs PCH PEI Policy initialization.
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@param[in, out] SiPolicy The SI Policy PPI instance
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@retval EFI_SUCCESS The PPI is installed and initialized.
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@retval EFI ERRORS The PPI is not successfully installed.
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@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
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**/
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EFI_STATUS
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EFIAPI
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UpdatePeiPchPolicy (
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IN OUT SI_POLICY_PPI *SiPolicy
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)
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{
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EFI_STATUS Status;
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UINT8 Index;
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DMI_HW_WIDTH_CONTROL *DmiHaAWC;
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PCH_GENERAL_CONFIG *PchGeneralConfig;
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PCH_PCIE_CONFIG *PcieRpConfig;
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PCH_SATA_CONFIG *SataConfig;
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PCH_IOAPIC_CONFIG *IoApicConfig;
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PCH_DMI_CONFIG *DmiConfig;
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PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig;
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PCH_HDAUDIO_CONFIG *HdAudioConfig;
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PCH_INTERRUPT_CONFIG *InterruptConfig;
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PCH_ISH_CONFIG *IshConfig;
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PCH_LAN_CONFIG *LanConfig;
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PCH_LOCK_DOWN_CONFIG *LockDownConfig;
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PCH_PM_CONFIG *PmConfig;
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PCH_SCS_CONFIG *ScsConfig;
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PCH_SERIAL_IO_CONFIG *SerialIoConfig;
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PCH_LPC_SIRQ_CONFIG *SerialIrqConfig;
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PCH_THERMAL_CONFIG *ThermalConfig;
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USB_CONFIG *UsbConfig;
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PCH_ESPI_CONFIG *EspiConfig;
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PCH_CNVI_CONFIG *CnviConfig;
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SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
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Status = GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOID *) &PcieRpConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *) &SataConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOID *) &IoApicConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *) &DmiConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigGuid, (VOID *) &FlashProtectionConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VOID *) &HdAudioConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (VOID *) &InterruptConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *) &IshConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *) &LanConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (VOID *) &LockDownConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &PmConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *) &ScsConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (VOID *) &SerialIrqConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VOID *) &ThermalConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) &UsbConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gEspiConfigGuid, (VOID *) &EspiConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID *) &CnviConfig);
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ASSERT_EFI_ERROR (Status);
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Status = PeiServicesLocatePpi (
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&gSiPreMemPolicyPpiGuid,
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0,
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NULL,
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(VOID **) &SiPreMemPolicyPpi
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);
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ASSERT_EFI_ERROR (Status);
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DmiConfig->PwrOptEnable = TRUE;
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PmConfig->PchSlpS3MinAssert = 0;
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PmConfig->PchSlpS4MinAssert = 0;
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PmConfig->PchSlpSusMinAssert = 0;
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PmConfig->PchSlpAMinAssert = 0;
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SataConfig->ThermalThrottling.P1T3M = 3;
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SataConfig->ThermalThrottling.P1T2M = 2;
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SataConfig->ThermalThrottling.P1T1M = 1;
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SataConfig->ThermalThrottling.P0T3M = 3;
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SataConfig->ThermalThrottling.P0T2M = 2;
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SataConfig->ThermalThrottling.P0T1M = 1;
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UpdatePcieClockInfo (PcieRpConfig, 0, PcdGet64 (PcdPcieClock0));
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UpdatePcieClockInfo (PcieRpConfig, 1, PcdGet64 (PcdPcieClock1));
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UpdatePcieClockInfo (PcieRpConfig, 2, PcdGet64 (PcdPcieClock2));
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UpdatePcieClockInfo (PcieRpConfig, 3, PcdGet64 (PcdPcieClock3));
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UpdatePcieClockInfo (PcieRpConfig, 4, PcdGet64 (PcdPcieClock4));
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UpdatePcieClockInfo (PcieRpConfig, 5, PcdGet64 (PcdPcieClock5));
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UpdatePcieClockInfo (PcieRpConfig, 6, PcdGet64 (PcdPcieClock6));
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UpdatePcieClockInfo (PcieRpConfig, 7, PcdGet64 (PcdPcieClock7));
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UpdatePcieClockInfo (PcieRpConfig, 8, PcdGet64 (PcdPcieClock8));
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UpdatePcieClockInfo (PcieRpConfig, 9, PcdGet64 (PcdPcieClock9));
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UpdatePcieClockInfo (PcieRpConfig, 10, PcdGet64 (PcdPcieClock10));
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UpdatePcieClockInfo (PcieRpConfig, 11, PcdGet64 (PcdPcieClock11));
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UpdatePcieClockInfo (PcieRpConfig, 12, PcdGet64 (PcdPcieClock12));
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UpdatePcieClockInfo (PcieRpConfig, 13, PcdGet64 (PcdPcieClock13));
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UpdatePcieClockInfo (PcieRpConfig, 14, PcdGet64 (PcdPcieClock14));
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UpdatePcieClockInfo (PcieRpConfig, 15, PcdGet64 (PcdPcieClock15));
|
|
PcieRpConfig->PcieDeviceOverrideTablePtr = (UINT32) mPcieDeviceTable;
|
PcieRpConfig->RootPort[0].ClkReqDetect = TRUE;
|
PcieRpConfig->RootPort[1].ClkReqDetect = TRUE;
|
PcieRpConfig->RootPort[2].ClkReqDetect = TRUE;
|
PcieRpConfig->RootPort[3].ClkReqDetect = TRUE;
|
PcieRpConfig->RootPort[4].ClkReqDetect = TRUE;
|
PcieRpConfig->RootPort[5].ClkReqDetect = TRUE;
|
PcieRpConfig->RootPort[6].ClkReqDetect = TRUE;
|
PcieRpConfig->RootPort[7].ClkReqDetect = TRUE;
|
PcieRpConfig->RootPort[8].ClkReqDetect = TRUE;
|
PcieRpConfig->RootPort[9].ClkReqDetect = TRUE;
|
PcieRpConfig->RootPort[10].ClkReqDetect = TRUE;
|
PcieRpConfig->RootPort[11].ClkReqDetect = TRUE;
|
PcieRpConfig->RootPort[12].ClkReqDetect = TRUE;
|
PcieRpConfig->RootPort[13].ClkReqDetect = TRUE;
|
PcieRpConfig->RootPort[14].ClkReqDetect = TRUE;
|
PcieRpConfig->RootPort[15].ClkReqDetect = TRUE;
|
PcieRpConfig->RootPort[0].AdvancedErrorReporting = TRUE;
|
PcieRpConfig->RootPort[1].AdvancedErrorReporting = TRUE;
|
PcieRpConfig->RootPort[2].AdvancedErrorReporting = TRUE;
|
PcieRpConfig->RootPort[3].AdvancedErrorReporting = TRUE;
|
PcieRpConfig->RootPort[4].AdvancedErrorReporting = TRUE;
|
PcieRpConfig->RootPort[5].AdvancedErrorReporting = TRUE;
|
PcieRpConfig->RootPort[6].AdvancedErrorReporting = TRUE;
|
PcieRpConfig->RootPort[7].AdvancedErrorReporting = TRUE;
|
PcieRpConfig->RootPort[8].AdvancedErrorReporting = TRUE;
|
PcieRpConfig->RootPort[9].AdvancedErrorReporting = TRUE;
|
PcieRpConfig->RootPort[10].AdvancedErrorReporting = TRUE;
|
PcieRpConfig->RootPort[11].AdvancedErrorReporting = TRUE;
|
PcieRpConfig->RootPort[12].AdvancedErrorReporting = TRUE;
|
PcieRpConfig->RootPort[13].AdvancedErrorReporting = TRUE;
|
PcieRpConfig->RootPort[14].AdvancedErrorReporting = TRUE;
|
PcieRpConfig->RootPort[15].AdvancedErrorReporting = TRUE;
|
|
//
|
// Install HDA Link/iDisplay Codec Verb Table
|
//
|
AddPlatformVerbTables (
|
PchHdaCodecPlatformOnboard,
|
&(HdAudioConfig->VerbTableEntryNum),
|
&(HdAudioConfig->VerbTablePtr)
|
);
|
|
LockDownConfig->BiosLock = FALSE;
|
LockDownConfig->BiosInterface = FALSE;
|
|
//
|
// IOAPIC Config
|
//
|
// IoApicConfig->IoApicEntry24_119 = PchSetup.PchIoApic24119Entries;
|
//
|
// To support SLP_S0, it's required to disable 8254 timer.
|
// Note that CSM may require this option to be disabled for correct operation.
|
// Once 8254 timer disabled, some legacy OPROM and legacy OS will fail while using 8254 timer.
|
// For some OS environment that it needs to set 8254CGE in late state it should
|
// set this policy to FALSE and use PmcSet8254ClockGateState (TRUE) in SMM later.
|
// This is also required during S3 resume.
|
//
|
// The Enable8254ClockGatingOnS3 is only applicable when Enable8254ClockGating is disabled.
|
// If Enable8254ClockGating is enabled, RC will do 8254 CGE programming on S3 as well.
|
// else, RC will do the programming on S3 when Enable8254ClockGatingOnS3 is enabled.
|
// This avoids the SMI requirement for the programming.
|
//
|
// If S0ix is not enabled, then disable 8254CGE for leagcy boot case.
|
//
|
IoApicConfig->Enable8254ClockGating = FALSE;
|
IoApicConfig->Enable8254ClockGatingOnS3 = FALSE;
|
|
//
|
// SerialIo Config
|
//
|
SerialIoConfig->DevMode[0] = 1;
|
SerialIoConfig->DevMode[1] = 1;
|
SerialIoConfig->DevMode[2] = 0;
|
SerialIoConfig->DevMode[3] = 0;
|
SerialIoConfig->DevMode[4] = 1;
|
SerialIoConfig->DevMode[5] = 0;
|
SerialIoConfig->DevMode[6] = 0;
|
SerialIoConfig->DevMode[7] = 0;
|
SerialIoConfig->DevMode[8] = 0;
|
SerialIoConfig->DevMode[9] = 0;
|
SerialIoConfig->DevMode[10] = 0;
|
SerialIoConfig->DevMode[11] = 3;
|
|
SerialIoConfig->Uart0PinMuxing = 1;
|
SerialIoConfig->SpiCsPolarity[0] = 1;
|
SerialIoConfig->SpiCsPolarity[1] = 0;
|
SerialIoConfig->SpiCsPolarity[2] = 0;
|
|
SerialIoConfig->UartHwFlowCtrl[0] = 1;
|
SerialIoConfig->UartHwFlowCtrl[1] = 1;
|
SerialIoConfig->UartHwFlowCtrl[2] = 1;
|
//
|
// I2C4 and I2C5 don't exist in SPT-H chipset
|
//
|
if (IsPchH ()) {
|
SerialIoConfig->DevMode[PchSerialIoIndexI2C4] = PchSerialIoDisabled;
|
SerialIoConfig->DevMode[PchSerialIoIndexI2C5] = PchSerialIoDisabled;
|
}
|
|
for (Index = 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++) {
|
SerialIoConfig->I2cPadsTermination[Index] = GetSerialIoI2cPadsTerminationFromPcd (Index);
|
}
|
|
PmConfig->SlpS0Override = 2; //PchSetup.SlpS0Override;
|
PmConfig->SlpS0DisQForDebug = 3; //PchSetup.SlpS0DisQForDebug;
|
PmConfig->SlpS0Vm075VSupport = 1; // PcdGetBool(PcdSlpS0Vm075VSupport);
|
PmConfig->CpuC10GatePinEnable = 1;
|
|
//
|
// Thermal Config
|
//
|
ThermalConfig->TsmicLock = TRUE;
|
ThermalConfig->PchHotEnable = PcdGetBool (PcdPchThermalHotEnable);
|
|
DmiHaAWC = &ThermalConfig->DmiHaAWC;
|
DmiHaAWC->TS3TW = 0;
|
DmiHaAWC->TS2TW = 1;
|
DmiHaAWC->TS1TW = 2;
|
DmiHaAWC->TS0TW = 3;
|
//
|
// Update Pch Usb Config
|
//
|
UpdatePchUsbConfig (
|
UsbConfig
|
);
|
|
ScsConfig->ScsUfsEnabled = 0;
|
ScsConfig->ScsEmmcHs400Enabled = 1;
|
ScsConfig->ScsEmmcHs400TuningRequired = TRUE;
|
|
IshConfig->I2c0GpioAssign = 1;
|
IshConfig->I2c1GpioAssign = 1;
|
IshConfig->Gp0GpioAssign = 1;
|
IshConfig->Gp1GpioAssign = 1;
|
IshConfig->Gp2GpioAssign = 1;
|
IshConfig->Gp3GpioAssign = 1;
|
IshConfig->Gp4GpioAssign = 1;
|
IshConfig->Gp5GpioAssign = 1;
|
IshConfig->Gp6GpioAssign = 1;
|
|
return Status;
|
}
|
