/** @file
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This file is SampleCode for Intel SA PEI Policy initialization.
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PeiSaPolicyInit.h"
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#include <Library/ConfigBlockLib.h>
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/**
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PcieCardResetWorkAround performs PCIe Card reset on root port
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@param[in out] SiPreMemPolicyPpi SI_PREMEM_POLICY_PPI
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@retval EFI_SUCCESS The policy is installed and initialized.
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**/
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EFI_STATUS
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PcieCardResetWorkAround (
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IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
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)
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{
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EFI_STATUS Status;
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SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
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SWITCHABLE_GRAPHICS_CONFIG *SgGpioData;
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Status = GetConfigBlock((VOID *)SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *)&MiscPeiPreMemConfig);
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ASSERT_EFI_ERROR(Status);
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Status = GetConfigBlock((VOID *)SiPreMemPolicyPpi, &gSwitchableGraphicsConfigGuid, (VOID *)&SgGpioData);
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ASSERT_EFI_ERROR(Status);
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if (SgGpioData->SaRtd3Pcie0Gpio.GpioSupport != NotSupported) {
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///
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/// dGPU is present.
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/// If PCIe Mode or SG Muxless
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/// Power on MXM
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/// Configure GPIOs to drive MXM in PCIe mode or SG Muxless
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/// else
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/// Do Nothing
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///
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if ((MiscPeiPreMemConfig->SgMode == SgModeMuxless) ||
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(MiscPeiPreMemConfig->SgMode == SgModeDgpu)) {
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DEBUG((DEBUG_INFO, "Configure GPIOs for driving the dGPU.\n"));
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///
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/// Drive DGPU HOLD RST Enable to make sure we hold reset
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///
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PcieGpioWrite (
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SgGpioData->SaRtd3Pcie0Gpio.HoldRst.GpioNo,
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SgGpioData->SaRtd3Pcie0Gpio.HoldRst.Active,
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GP_ENABLE
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);
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///
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/// wait 100ms
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///
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MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterHoldReset) * STALL_ONE_MILLI_SECOND);
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///
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/// Drive DGPU PWR EN to Power On MXM
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///
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PcieGpioWrite (
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SgGpioData->SaRtd3Pcie0Gpio.PwrEnable.GpioNo,
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SgGpioData->SaRtd3Pcie0Gpio.PwrEnable.Active,
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GP_ENABLE
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);
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///
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/// wait 300ms
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///
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MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterPwrEn) * STALL_ONE_MILLI_SECOND);
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///
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/// Drive DGPU HOLD RST Disabled to remove reset
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///
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PcieGpioWrite (
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SgGpioData->SaRtd3Pcie0Gpio.HoldRst.GpioNo,
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SgGpioData->SaRtd3Pcie0Gpio.HoldRst.Active,
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GP_DISABLE
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);
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///
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/// wait 100ms
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///
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MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterHoldReset) * STALL_ONE_MILLI_SECOND);
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}
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}
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return EFI_SUCCESS;
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}
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/**
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PCIe GPIO Write
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@param[in] Gpio - GPIO Number
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@param[in] Active - GPIO Active Information; High/Low
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@param[in] Level - Write GPIO value (0/1)
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**/
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VOID
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PcieGpioWrite (
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IN UINT32 Gpio,
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IN BOOLEAN Active,
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IN BOOLEAN Level
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)
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{
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EFI_STATUS Status;
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if (Active == 0) {
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Level = (~Level) & 0x1;
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}
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Status = GpioSetOutputValue(Gpio, (UINT32)Level);
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if (Status != EFI_SUCCESS) {
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return;
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}
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}
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