/** @file
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` Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// Module specific Includes
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//
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#include <Library/BaseMemoryLib.h>
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#include <Library/BaseLib.h>
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#include <Library/GpioLib.h>
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#include <TbtBoardInfo.h>
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#include <Protocol/TbtNvsArea.h>
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#include <PchAccess.h>
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#include <Library/BaseLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/IoLib.h>
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#include <Library/SmmServicesTableLib.h>
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#include <Protocol/SmmSxDispatch2.h>
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#include <Protocol/SmmSwDispatch2.h>
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#include <Uefi/UefiSpec.h>
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#include <Library/UefiLib.h>
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#include <Library/UefiRuntimeServicesTableLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Guid/HobList.h>
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#include "TbtSmiHandler.h"
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#include <PcieRegs.h>
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#include <Protocol/SaPolicy.h>
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#include <Protocol/DxeTbtPolicy.h>
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#include <Library/PchPmcLib.h>
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#define P2P_BRIDGE (((PCI_CLASS_BRIDGE) << 8) | (PCI_CLASS_BRIDGE_P2P))
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#define CMD_BM_MEM_IO (CMD_BUS_MASTER | BIT1 | BIT0)
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#define DISBL_IO_REG1C 0x01F1
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#define DISBL_MEM32_REG20 0x0000FFF0
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#define DISBL_PMEM_REG24 0x0001FFF1
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#define DOCK_BUSSES 8
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#define PCI_CAPABILITY_ID_PCIEXP 0x10
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#define PCI_CAPBILITY_POINTER_OFFSET 0x34
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#define LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recommended maximum value for Snoop Latency can we put like this ?
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#define LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recommended maximum value for Non-Snoop Latency can we put like this ?
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GLOBAL_REMOVE_IF_UNREFERENCED TBT_NVS_AREA *mTbtNvsAreaPtr;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gCurrentDiscreteTbtRootPort;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gCurrentDiscreteTbtRootPortType;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT16 TbtLtrMaxSnoopLatency;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT16 TbtLtrMaxNoSnoopLatency;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gDTbtPcieRstSupport;
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GLOBAL_REMOVE_IF_UNREFERENCED TBT_INFO_HOB *gTbtInfoHob = NULL;
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STATIC UINTN mPciExpressBaseAddress;
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STATIC UINT8 TbtSegment = 0;
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VOID
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GpioWrite (
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IN UINT32 GpioNumber,
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IN BOOLEAN Value
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)
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{
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GpioSetOutputValue (GpioNumber, (UINT32)Value);
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}
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/**
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Search and return the offset of desired Pci Express Capability ID
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CAPID list:
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0x0001 = Advanced Error Reporting Capability
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0x0002 = Virtual Channel Capability
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0x0003 = Device Serial Number Capability
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0x0004 = Power Budgeting Capability
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@param[in] Bus Pci Bus Number
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@param[in] Device Pci Device Number
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@param[in] Function Pci Function Number
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@param[in] CapId Extended CAPID to search for
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@retval 0 CAPID not found
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@retval Other CAPID found, Offset of desired CAPID
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**/
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UINT16
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PcieFindExtendedCapId (
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Function,
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IN UINT16 CapId
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)
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{
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UINT16 CapHeaderOffset;
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UINT16 CapHeaderId;
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UINT64 DeviceBase;
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DeviceBase = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, Function, 0);
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///
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/// Start to search at Offset 0x100
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/// Get Capability Header, A pointer value of 00h is used to indicate the last capability in the list.
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///
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CapHeaderId = 0;
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CapHeaderOffset = 0x100;
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while (CapHeaderOffset != 0 && CapHeaderId != 0xFFFF) {
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CapHeaderId = PciSegmentRead16 (DeviceBase + CapHeaderOffset);
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if (CapHeaderId == CapId) {
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return CapHeaderOffset;
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}
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///
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/// Each capability must be DWORD aligned.
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/// The bottom two bits of all pointers are reserved and must be implemented as 00b
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/// although software must mask them to allow for future uses of these bits.
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///
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CapHeaderOffset = (PciSegmentRead16 (DeviceBase + CapHeaderOffset + 2) >> 4) & ((UINT16) ~(BIT0 | BIT1));
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}
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return 0;
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}
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/**
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Find the Offset to a given Capabilities ID
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CAPID list:
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0x01 = PCI Power Management Interface
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0x04 = Slot Identification
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0x05 = MSI Capability
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0x10 = PCI Express Capability
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@param[in] Bus Pci Bus Number
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@param[in] Device Pci Device Number
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@param[in] Function Pci Function Number
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@param[in] CapId CAPID to search for
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@retval 0 CAPID not found
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@retval Other CAPID found, Offset of desired CAPID
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**/
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UINT8
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PcieFindCapId (
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IN UINT8 Segment,
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Function,
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IN UINT8 CapId
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)
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{
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UINT8 CapHeaderOffset;
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UINT8 CapHeaderId;
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UINT64 DeviceBase;
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DeviceBase = PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, Function, 0);
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if ((PciSegmentRead8 (DeviceBase + PCI_PRIMARY_STATUS_OFFSET) & EFI_PCI_STATUS_CAPABILITY) == 0x00) {
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///
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/// Function has no capability pointer
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///
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return 0;
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}
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///
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/// Check the header layout to determine the Offset of Capabilities Pointer Register
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///
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if ((PciSegmentRead8 (DeviceBase + PCI_HEADER_TYPE_OFFSET) & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE)) {
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///
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/// If CardBus bridge, start at Offset 0x14
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///
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CapHeaderOffset = 0x14;
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} else {
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///
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/// Otherwise, start at Offset 0x34
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///
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CapHeaderOffset = 0x34;
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}
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///
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/// Get Capability Header, A pointer value of 00h is used to indicate the last capability in the list.
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///
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CapHeaderId = 0;
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CapHeaderOffset = PciSegmentRead8 (DeviceBase + CapHeaderOffset) & ((UINT8) ~(BIT0 | BIT1));
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while (CapHeaderOffset != 0 && CapHeaderId != 0xFF) {
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CapHeaderId = PciSegmentRead8 (DeviceBase + CapHeaderOffset);
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if (CapHeaderId == CapId) {
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return CapHeaderOffset;
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}
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///
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/// Each capability must be DWORD aligned.
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/// The bottom two bits of all pointers (including the initial pointer at 34h) are reserved
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/// and must be implemented as 00b although software must mask them to allow for future uses of these bits.
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///
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CapHeaderOffset = PciSegmentRead8 (DeviceBase + CapHeaderOffset + 1) & ((UINT8) ~(BIT0 | BIT1));
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}
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return 0;
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}
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/**
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This function configures the L1 Substates.
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It can be used for Rootport and endpoint devices.
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@param[in] DownstreamPort Indicates if the device about to be programmed is a downstream port
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@param[in] DeviceBase Device PCI configuration base address
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@param[in] L1SubstateExtCapOffset Pointer to L1 Substate Capability Structure
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@param[in] PortL1SubstateCapSupport L1 Substate capability setting
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@param[in] PortCommonModeRestoreTime Common Mode Restore Time
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@param[in] PortTpowerOnValue Tpower_on Power On Wait Time
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@param[in] PortTpowerOnScale Tpower-on Scale
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@retval none
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**/
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VOID
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ConfigureL1s (
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IN UINTN DeviceBase,
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IN UINT16 L1SubstateExtCapOffset,
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IN UINT32 PortL1SubstateCapSupport,
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IN UINT32 PortCommonModeRestoreTime,
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IN UINT32 PortTpowerOnValue,
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IN UINT32 PortTpowerOnScale,
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IN UINT16 MaxLevel
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)
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{
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PciSegmentAndThenOr32 (
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DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
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(UINT32) ~(0xFF00),
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(UINT32) PortCommonModeRestoreTime << 8
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);
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PciSegmentAnd32(DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL2_OFFSET, 0xFFFFFF04);
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PciSegmentOr32(DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL2_OFFSET,(UINT32) ((PortTpowerOnValue << N_PCIE_EX_L1SCTL2_POWT) | PortTpowerOnScale));
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PciSegmentAndThenOr32 (
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DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
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(UINT32) ~(0xE3FF0000),
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(UINT32) (BIT30 | BIT23 | BIT21)
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);
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}
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VOID
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RootportL1sSupport (
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IN UINT8 Bus,
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IN UINT8 Dev,
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IN UINT8 Fun,
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IN UINT16 RootL1SubstateExtCapOffset,
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IN UINT16 MaxL1Level
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)
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{
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UINTN ComponentABaseAddress;
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UINTN ComponentBBaseAddress;
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UINT8 SecBus;
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UINT32 PortL1SubstateCapSupport;
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UINT32 PortCommonModeRestoreTime;
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UINT32 PortTpowerOnValue;
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UINT32 PortTpowerOnScale;
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UINT16 ComponentBL1SubstateExtCapOffset;
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UINT32 ComponentBL1Substates;
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UINT32 ComponentBCommonModeRestoreTime;
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UINT32 ComponentBTpowerOnValue;
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UINT32 ComponentBTpowerOnScale;
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UINT32 Data32;
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PortL1SubstateCapSupport = 0;
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PortCommonModeRestoreTime = 0;
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PortTpowerOnValue = 0;
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PortTpowerOnScale = 0;
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Data32 = 0;
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ComponentABaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
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if (RootL1SubstateExtCapOffset != 0) {
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Data32 = PciSegmentRead32 (ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX_L1SCAP_OFFSET);
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PortL1SubstateCapSupport = (Data32) & 0x0F;
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PortCommonModeRestoreTime = (Data32 >> 8) & 0xFF;
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PortTpowerOnScale = (Data32 >> 16) & 0x3;
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PortTpowerOnValue = (Data32 >> 19) & 0x1F;
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} else {
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MaxL1Level = 0; // If L1 Substates from Root Port side is disable, then Disable from Device side also.
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}
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SecBus = PciSegmentRead8 (ComponentABaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
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ComponentBBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, SecBus, 0, 0, 0);
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if (PciSegmentRead16 (ComponentBBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
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ComponentBL1SubstateExtCapOffset = PcieFindExtendedCapId (
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SecBus,
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0,
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0,
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V_PCIE_EX_L1S_CID
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);
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if (ComponentBL1SubstateExtCapOffset != 0) {
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ComponentBL1Substates = PciSegmentRead32 (ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_PCIE_EX_L1SCAP_OFFSET);
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ComponentBCommonModeRestoreTime = (ComponentBL1Substates >> 8) & 0xFF;
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ComponentBTpowerOnScale = (ComponentBL1Substates >> 16) & 0x3;
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ComponentBTpowerOnValue = (ComponentBL1Substates >> 19) & 0x1F;
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if (MaxL1Level == 3) {
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if (Data32 >= ComponentBL1Substates) {
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if (~(Data32 | BIT2)) {
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MaxL1Level = 1;
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}
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}
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else {
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if (~(ComponentBL1Substates | BIT2)) {
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MaxL1Level = 1;
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}
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}
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}
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if (MaxL1Level == 3) {
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ConfigureL1s (
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ComponentABaseAddress,
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RootL1SubstateExtCapOffset,
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PortL1SubstateCapSupport,
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ComponentBCommonModeRestoreTime,
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ComponentBTpowerOnValue,
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ComponentBTpowerOnScale,
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MaxL1Level
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);
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ConfigureL1s (
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ComponentBBaseAddress,
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ComponentBL1SubstateExtCapOffset,
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ComponentBL1Substates,
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PortCommonModeRestoreTime,
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PortTpowerOnValue,
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PortTpowerOnScale,
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MaxL1Level
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);
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}
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if (MaxL1Level == 1) {
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PciSegmentOr32 (
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ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
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(UINT32) (BIT3 | BIT1)
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);
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PciSegmentOr32 (
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ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
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(UINT32) (BIT3 | BIT1)
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);
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}
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else {
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if (RootL1SubstateExtCapOffset != 0) {
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PciSegmentOr32 (
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ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
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(UINT32) (BIT3 | BIT1)
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);
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PciSegmentOr32 (
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ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
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(UINT32) (BIT2 | BIT0)
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);
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}
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if (ComponentBL1SubstateExtCapOffset != 0) {
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PciSegmentOr32 (
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ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
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(UINT32) (BIT3 | BIT1)
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);
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PciSegmentOr32 (
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ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
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(UINT32) (BIT2 | BIT0)
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);
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}
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}
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}
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}
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}
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VOID
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MultiFunctionDeviceAspm (
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IN UINT8 Bus,
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IN UINT8 Dev
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)
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{
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UINT16 LowerAspm;
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UINT16 AspmVal;
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UINT8 Fun;
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UINT64 DeviceBaseAddress;
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UINT8 CapHeaderOffset;
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LowerAspm = 3; // L0s and L1 Supported
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for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
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//
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// Check for Device availability
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//
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DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
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if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
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// Device not present
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continue;
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}
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CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10);
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AspmVal = (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x00C) >> 10) & 3;
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if (LowerAspm > AspmVal) {
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LowerAspm = AspmVal;
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}
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} //Fun
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for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
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//
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// Check for Device availability
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//
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DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
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if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
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//
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// Device not present
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//
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continue;
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}
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CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10);
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PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFFC, LowerAspm);
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} //Fun
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}
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UINT16
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LimitAspmLevel (
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IN UINT16 SelectedAspm,
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IN UINT16 MaxAspmLevel
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)
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{
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SelectedAspm = SelectedAspm & MaxAspmLevel;
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return SelectedAspm;
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}
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UINT16
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FindOptimalAspm (
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IN UINT16 ComponentAaspm,
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IN UINT16 ComponentBaspm
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)
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{
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UINT16 SelectedAspm;
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SelectedAspm = ComponentAaspm & ComponentBaspm;
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return SelectedAspm;
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}
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UINT16
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FindComponentBaspm (
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IN UINT8 Bus,
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IN UINT8 MaxBus
|
)
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{
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UINT8 BusNo;
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UINT8 DevNo;
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UINT8 FunNo;
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UINT64 DevBaseAddress;
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UINT8 RegVal;
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UINT8 SecBusNo;
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UINT16 SelectedAspm; // No ASPM Support
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UINT8 CapHeaderOffset_B;
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BOOLEAN AspmFound;
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SelectedAspm = 0;
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AspmFound = FALSE;
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for (BusNo = MaxBus; (BusNo != 0xFF) && (!AspmFound); --BusNo) {
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for (DevNo = 0; (DevNo <= PCI_MAX_DEVICE) && (!AspmFound); ++DevNo) {
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for (FunNo = 0; (FunNo <= PCI_MAX_FUNC) && (!AspmFound); ++FunNo) {
|
//
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// Check for Device availability
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//
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DevBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, BusNo, DevNo, FunNo, 0);
|
if (PciSegmentRead16 (DevBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
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//
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// Device not present
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//
|
continue;
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}
|
|
RegVal = PciSegmentRead8 (DevBaseAddress + PCI_HEADER_TYPE_OFFSET);
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if ((RegVal & (BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6)) != 0x01) {
|
//
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// Not a PCI-to-PCI bridges device
|
//
|
continue;
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}
|
|
SecBusNo = PciSegmentRead8 (DevBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
|
|
if (SecBusNo == Bus) {
|
//
|
// This is the Rootbridge for the given 'Bus' device
|
//
|
CapHeaderOffset_B = PcieFindCapId (TbtSegment, BusNo, DevNo, FunNo, 0x10);
|
SelectedAspm = (PciSegmentRead16 (DevBaseAddress + CapHeaderOffset_B + 0x00C) >> 10) & 3;
|
AspmFound = TRUE;
|
}
|
} //FunNo
|
} //DevNo
|
} //BusNo
|
|
return (SelectedAspm);
|
}
|
|
VOID
|
NoAspmSupport (
|
IN UINT8 Bus,
|
IN UINT8 Dev,
|
IN UINT8 Fun,
|
IN UINT8 CapHeaderOffset
|
)
|
{
|
UINT64 DeviceBaseAddress;
|
|
DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
|
PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFFC, 0x00);
|
}
|
|
VOID
|
EndpointAspmSupport (
|
IN UINT8 Bus,
|
IN UINT8 Dev,
|
IN UINT8 Fun,
|
IN UINT8 CapHeaderOffset,
|
IN UINT8 MaxBus,
|
IN UINT16 MaxAspmLevel
|
)
|
{
|
UINT64 DeviceBaseAddress;
|
UINT16 ComponentAaspm;
|
UINT16 ComponentBaspm;
|
UINT16 SelectedAspm;
|
|
DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
|
ComponentAaspm = (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x00C) >> 10) & 3;
|
ComponentBaspm = FindComponentBaspm (Bus, MaxBus);
|
SelectedAspm = FindOptimalAspm (ComponentAaspm, ComponentBaspm);
|
SelectedAspm = LimitAspmLevel (SelectedAspm, MaxAspmLevel);
|
PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFFC, SelectedAspm);
|
}
|
|
VOID
|
UpstreamAspmSupport (
|
IN UINT8 Bus,
|
IN UINT8 Dev,
|
IN UINT8 Fun,
|
IN UINT8 CapHeaderOffset,
|
IN UINT8 MaxBus,
|
IN UINT16 MaxAspmLevel
|
)
|
{
|
UINT64 DeviceBaseAddress;
|
UINT16 ComponentAaspm;
|
UINT16 ComponentBaspm;
|
UINT16 SelectedAspm;
|
|
DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
|
ComponentAaspm = (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x00C) >> 10) & 3;
|
ComponentBaspm = FindComponentBaspm (Bus, MaxBus);
|
SelectedAspm = FindOptimalAspm (ComponentAaspm, ComponentBaspm);
|
SelectedAspm = LimitAspmLevel (SelectedAspm, MaxAspmLevel);
|
PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFFC, SelectedAspm);
|
}
|
|
VOID
|
DownstreamAspmSupport (
|
IN UINT8 Bus,
|
IN UINT8 Dev,
|
IN UINT8 Fun,
|
IN UINT8 CapHeaderOffset,
|
IN UINT16 MaxAspmLevel
|
)
|
{
|
UINT64 ComponentABaseAddress;
|
UINT64 ComponentBBaseAddress;
|
UINT16 ComponentAaspm;
|
UINT16 ComponentBaspm;
|
UINT16 SelectedAspm;
|
UINT8 SecBus;
|
UINT8 CapHeaderOffset_B;
|
|
ComponentABaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
|
ComponentAaspm = (PciSegmentRead16 (ComponentABaseAddress + CapHeaderOffset + 0x00C) >> 10) & 3;
|
|
SecBus = PciSegmentRead8 (ComponentABaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
|
ComponentBBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, SecBus, 0, 0, 0);
|
ComponentBaspm = 0; // No ASPM Support
|
if (PciSegmentRead16 (ComponentBBaseAddress + PCI_DEVICE_ID_OFFSET) != 0xFFFF) {
|
CapHeaderOffset_B = PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10);
|
ComponentBaspm = (PciSegmentRead16 (ComponentBBaseAddress + CapHeaderOffset_B + 0x00C) >> 10) & 3;
|
}
|
|
SelectedAspm = FindOptimalAspm (ComponentAaspm, ComponentBaspm);
|
SelectedAspm = LimitAspmLevel (SelectedAspm, MaxAspmLevel);
|
PciSegmentAndThenOr16 (ComponentABaseAddress + CapHeaderOffset + 0x10, 0xFFFC, SelectedAspm);
|
}
|
|
VOID
|
RootportAspmSupport (
|
IN UINT8 Bus,
|
IN UINT8 Dev,
|
IN UINT8 Fun,
|
IN UINT8 CapHeaderOffset,
|
IN UINT16 MaxAspmLevel
|
)
|
{
|
UINT64 ComponentABaseAddress;
|
UINT64 ComponentBBaseAddress;
|
UINT16 ComponentAaspm;
|
UINT16 ComponentBaspm;
|
UINT16 SelectedAspm;
|
UINT8 SecBus;
|
UINT8 CapHeaderOffset_B;
|
|
ComponentABaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
|
ComponentAaspm = (PciSegmentRead16 (ComponentABaseAddress + CapHeaderOffset + 0x00C) >> 10) & 3;
|
|
SecBus = PciSegmentRead8 (ComponentABaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
|
ComponentBBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, SecBus, 0, 0, 0);
|
ComponentBaspm = 0; // No ASPM Support
|
if (PciSegmentRead16 (ComponentBBaseAddress + PCI_DEVICE_ID_OFFSET) != 0xFFFF) {
|
CapHeaderOffset_B = PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10);
|
ComponentBaspm = (PciSegmentRead16 (ComponentBBaseAddress + CapHeaderOffset_B + 0x00C) >> 10) & 3;
|
}
|
|
SelectedAspm = FindOptimalAspm (ComponentAaspm, ComponentBaspm);
|
SelectedAspm = LimitAspmLevel (SelectedAspm, MaxAspmLevel);
|
PciSegmentAndThenOr16 (ComponentABaseAddress + CapHeaderOffset + 0x10, 0xFFFC, SelectedAspm);
|
}
|
|
VOID
|
ThunderboltEnableAspmWithoutLtr (
|
IN UINT16 MaxAspmLevel,
|
IN UINTN RpSegment,
|
IN UINTN RpBus,
|
IN UINTN RpDevice,
|
IN UINTN RpFunction
|
)
|
{
|
UINT8 Bus;
|
UINT8 Dev;
|
UINT8 Fun;
|
UINT8 RootBus;
|
UINT8 RootDev;
|
UINT8 RootFun;
|
UINT8 MinBus;
|
UINT8 MaxBus;
|
UINT16 DeviceId;
|
UINT64 DeviceBaseAddress;
|
UINT8 RegVal;
|
UINT8 CapHeaderOffset;
|
UINT16 DevicePortType;
|
|
MinBus = 0;
|
MaxBus = 0;
|
|
MinBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
|
MaxBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
|
DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinBus, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
|
if (!(IsTbtHostRouter (DeviceId))) {
|
return;
|
}
|
|
TbtSegment = (UINT8)RpSegment;
|
|
RootBus = (UINT8)RpBus;
|
RootDev = (UINT8)RpDevice;
|
RootFun = (UINT8)RpFunction;
|
|
//
|
// Enumerate all the bridges and devices which are available on TBT host controller
|
//
|
for (Bus = MinBus; Bus <= MaxBus; ++Bus) {
|
for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
|
//
|
// Check for Device availability
|
//
|
DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, 0, 0);
|
if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
|
//
|
// Device not present
|
//
|
continue;
|
}
|
|
RegVal = PciSegmentRead8 (DeviceBaseAddress + PCI_HEADER_TYPE_OFFSET);
|
if ((RegVal & BIT7) == 0) {
|
//
|
// Not a multi-function device
|
//
|
continue;
|
}
|
|
MultiFunctionDeviceAspm(Bus, Dev);
|
} //Dev
|
} //Bus
|
|
|
for (Bus = MinBus; Bus <= MaxBus; ++Bus) {
|
for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
|
for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
|
//
|
// Check for Device availability
|
//
|
DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
|
if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
|
//
|
// Device not present
|
//
|
continue;
|
}
|
|
CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10);
|
DevicePortType = (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x002) >> 4) & 0xF;
|
if(PciSegmentRead8 (DeviceBaseAddress + PCI_CLASSCODE_OFFSET) == PCI_CLASS_SERIAL) {
|
MaxAspmLevel = (UINT16) 0x1;
|
}
|
|
switch (DevicePortType) {
|
case 0:
|
//
|
// PCI Express Endpoint
|
//
|
EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, MaxAspmLevel);
|
break;
|
|
case 1:
|
//
|
// Legacy PCI Express Endpoint
|
//
|
EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, MaxAspmLevel);
|
break;
|
|
case 4:
|
//
|
// Root Port of PCI Express Root Complex
|
//
|
RootportAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxAspmLevel);
|
break;
|
|
case 5:
|
//
|
// Upstream Port of PCI Express Switch
|
//
|
UpstreamAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, MaxAspmLevel);
|
break;
|
|
case 6:
|
//
|
// Downstream Port of PCI Express Switch
|
//
|
DownstreamAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxAspmLevel);
|
break;
|
|
case 7:
|
//
|
// PCI Express to PCI/PCI-X Bridge
|
//
|
NoAspmSupport (Bus, Dev, Fun, CapHeaderOffset);
|
break;
|
|
case 8:
|
//
|
// PCI/PCI-X to PCI Express Bridge
|
//
|
NoAspmSupport (Bus, Dev, Fun, CapHeaderOffset);
|
break;
|
|
case 9:
|
//
|
// Root Complex Integrated Endpoint
|
//
|
EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, MaxAspmLevel);
|
break;
|
|
case 10:
|
//
|
// Root Complex Event Collector
|
//
|
EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, MaxAspmLevel);
|
break;
|
|
default:
|
break;
|
}
|
//
|
// switch(DevicePortType)
|
//
|
}
|
//
|
// Fun
|
//
|
}
|
//
|
// Dev
|
//
|
}
|
//
|
// Bus
|
//
|
CapHeaderOffset = PcieFindCapId (TbtSegment, RootBus, RootDev, RootFun, 0x10);
|
RootportAspmSupport (RootBus, RootDev, RootFun, CapHeaderOffset, MaxAspmLevel);
|
}
|
|
|
|
VOID
|
ThunderboltEnableL1Sub (
|
IN UINT16 MaxL1Level,
|
IN UINTN RpSegment,
|
IN UINTN RpBus,
|
IN UINTN RpDevice,
|
IN UINTN RpFunction
|
)
|
{
|
UINT16 CapHeaderOffsetExtd;
|
|
RpBus = 0;
|
|
CapHeaderOffsetExtd = PcieFindExtendedCapId ((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunction, V_PCIE_EX_L1S_CID);
|
RootportL1sSupport ((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunction, CapHeaderOffsetExtd, MaxL1Level);
|
}
|
|
VOID
|
ThunderboltDisableAspmWithoutLtr (
|
IN UINTN RpSegment,
|
IN UINTN RpBus,
|
IN UINTN RpDevice,
|
IN UINTN RpFunction
|
)
|
{
|
UINT8 Bus;
|
UINT8 Dev;
|
UINT8 Fun;
|
UINT8 RootBus;
|
UINT8 RootDev;
|
UINT8 RootFun;
|
UINT8 MinBus;
|
UINT8 MaxBus;
|
UINT16 DeviceId;
|
UINT64 DeviceBaseAddress;
|
UINT8 CapHeaderOffset;
|
|
MinBus = 0;
|
MaxBus = 0;
|
|
MinBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
|
MaxBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
|
DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinBus, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
|
if (!(IsTbtHostRouter (DeviceId))) {
|
return;
|
}
|
|
TbtSegment = (UINT8)RpSegment;
|
RootBus = (UINT8)RpBus;
|
RootDev = (UINT8)RpDevice;
|
RootFun = (UINT8)RpFunction;
|
|
//
|
// Enumerate all the bridges and devices which are available on TBT host controller
|
//
|
for (Bus = MinBus; Bus <= MaxBus; ++Bus) {
|
for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
|
for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
|
//
|
// Check for Device availability
|
//
|
DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
|
if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
|
//
|
// Device not present
|
//
|
continue;
|
}
|
|
CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10);
|
PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFFC, 0x00);
|
} //Fun
|
} //Dev
|
} //Bus
|
|
CapHeaderOffset = PcieFindCapId (TbtSegment, RootBus, RootDev, RootFun, 0x10);
|
NoAspmSupport(RootBus, RootDev, RootFun, CapHeaderOffset);
|
}
|
|
VOID
|
TbtProgramClkReq (
|
IN UINT8 Bus,
|
IN UINT8 Device,
|
IN UINT8 Function,
|
IN UINT8 ClkReqSetup
|
)
|
{
|
UINT64 DeviceBaseAddress;
|
UINT8 CapHeaderOffset;
|
UINT16 Data16;
|
|
DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, Function, 0);
|
CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Device, Function, 0x10);
|
|
//
|
// Check if CLKREQ# is supported
|
//
|
if ((PciSegmentRead32 (DeviceBaseAddress + CapHeaderOffset + 0x0C) & BIT18) != 0) {
|
Data16 = PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x010);
|
|
if (ClkReqSetup) {
|
Data16 = Data16 | BIT8; // Enable Clock Power Management
|
} else {
|
Data16 = Data16 & (UINT16)(~BIT8); // Disable Clock Power Management
|
}
|
|
PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffset + 0x010, Data16);
|
}
|
}
|
VOID
|
TbtProgramPtm(
|
IN UINT8 Bus,
|
IN UINT8 Device,
|
IN UINT8 Function,
|
IN UINT8 PtmSetup,
|
IN BOOLEAN IsRoot
|
)
|
{
|
UINT64 DeviceBaseAddress;
|
UINT16 CapHeaderOffset;
|
UINT16 PtmControlRegister;
|
UINT16 PtmCapabilityRegister;
|
|
DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS(TbtSegment, Bus, Device, Function, 0);
|
CapHeaderOffset = PcieFindExtendedCapId(Bus, Device, Function, 0x001F /*V_PCIE_EX_PTM_CID*/);
|
if(CapHeaderOffset != 0) {
|
PtmCapabilityRegister = PciSegmentRead16(DeviceBaseAddress + CapHeaderOffset + 0x04);
|
//
|
// Check if PTM Requester/ Responder capability for the EP/Down stream etc
|
//
|
if ((PtmCapabilityRegister & (BIT1 | BIT0)) != 0) {
|
PtmControlRegister = PciSegmentRead16(DeviceBaseAddress + CapHeaderOffset + 0x08);
|
|
if (PtmSetup) {
|
PtmControlRegister = PtmControlRegister | BIT0; // Enable PTM
|
if(IsRoot) {
|
PtmControlRegister = PtmControlRegister | BIT1; // Enable PTM
|
}
|
PtmControlRegister = PtmControlRegister | (PtmCapabilityRegister & 0xFF00); // Programm Local Clock Granularity
|
} else {
|
PtmControlRegister = PtmControlRegister & (UINT16)(~(BIT0 | BIT1)); // Disable Clock Power Management
|
}
|
|
PciSegmentWrite16(DeviceBaseAddress + CapHeaderOffset + 0x08, PtmControlRegister);
|
}
|
}
|
}
|
|
VOID
|
ConfigureTbtPm (
|
IN UINTN RpSegment,
|
IN UINTN RpBus,
|
IN UINTN RpDevice,
|
IN UINTN RpFunction,
|
IN UINT8 Configuration // 1- Clk Request , 2- PTM ,
|
)
|
{
|
UINT8 Bus;
|
UINT8 Dev;
|
UINT8 Fun;
|
UINT8 MinBus;
|
UINT8 MaxBus;
|
UINT16 DeviceId;
|
UINT64 DeviceBaseAddress;
|
|
MinBus = 0;
|
MaxBus = 0;
|
|
if ((Configuration != 1) && (Configuration != 2)) {
|
return;
|
}
|
MinBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
|
MaxBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
|
DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinBus, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
|
if (!(IsTbtHostRouter (DeviceId))) {
|
return;
|
}
|
|
TbtSegment = (UINT8)RpSegment;
|
//
|
// Enumerate all the bridges and devices which are available on TBT host controller
|
//
|
for (Bus = MaxBus; Bus >= MinBus; --Bus) {
|
for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
|
for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
|
//
|
// Check for Device availability
|
//
|
DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
|
if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
|
if (Fun == 0) {
|
//
|
// IF Fun is zero, stop enumerating other functions of the particular bridge
|
//
|
break;
|
}
|
//
|
// otherwise, just skip checking for CLKREQ support
|
//
|
continue;
|
}
|
switch (Configuration) {
|
case 1:
|
TbtProgramClkReq (Bus, Dev, Fun, (UINT8) mTbtNvsAreaPtr->TbtSetClkReq);
|
break;
|
case 2:
|
TbtProgramPtm (Bus, Dev, Fun, (UINT8) mTbtNvsAreaPtr->TbtPtm, FALSE);
|
TbtProgramPtm((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunction, (UINT8) mTbtNvsAreaPtr->TbtPtm, TRUE);
|
break;
|
default:
|
break;
|
}
|
} //Fun
|
} // Dev
|
} // Bus
|
}
|
|
/**
|
1) Check LTR support in device capabilities 2 register (bit 11).
|
2) If supported enable LTR in device control 2 register (bit 10).
|
|
**/
|
VOID
|
TbtProgramLtr (
|
IN UINT8 Bus,
|
IN UINT8 Device,
|
IN UINT8 Function,
|
IN UINT8 LtrSetup
|
)
|
{
|
UINT64 DeviceBaseAddress;
|
UINT8 CapHeaderOffset;
|
UINT16 Data16;
|
|
DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, Function, 0);
|
CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Device, Function, 0x10);
|
|
//
|
// Check if LTR# is supported
|
//
|
if ((PciSegmentRead32 (DeviceBaseAddress + CapHeaderOffset + 0x24) & BIT11) != 0) {
|
Data16 = PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x028);
|
|
if (LtrSetup) {
|
Data16 = Data16 | BIT10; // LTR Mechanism Enable
|
} else {
|
Data16 = Data16 & (UINT16)(~BIT10); // LTR Mechanism Disable
|
}
|
|
PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffset + 0x028, Data16);
|
}
|
}
|
|
VOID
|
ConfigureLtr (
|
IN UINTN RpSegment,
|
IN UINTN RpBus,
|
IN UINTN RpDevice,
|
IN UINTN RpFunction
|
)
|
{
|
UINT8 Bus;
|
UINT8 Dev;
|
UINT8 Fun;
|
UINT8 MinBus;
|
UINT8 MaxBus;
|
UINT16 DeviceId;
|
UINT64 DeviceBaseAddress;
|
|
MinBus = 0;
|
MaxBus = 0;
|
|
MinBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
|
MaxBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
|
DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinBus, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
|
if (!(IsTbtHostRouter (DeviceId))) {
|
return;
|
}
|
|
TbtSegment = (UINT8)RpSegment;
|
//
|
// Enumerate all the bridges and devices which are available on TBT host controller
|
//
|
for (Bus = MinBus; Bus <= MaxBus; ++Bus) {
|
for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
|
for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
|
//
|
// Check for Device availability
|
//
|
DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
|
if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
|
if (Fun == 0) {
|
//
|
// IF Fun is zero, stop enumerating other functions of the particular bridge
|
//
|
break;
|
}
|
//
|
// otherwise, just skip checking for LTR support
|
//
|
continue;
|
}
|
|
TbtProgramLtr (Bus, Dev, Fun, (UINT8) mTbtNvsAreaPtr->TbtLtr);
|
|
} //Fun
|
} // Dev
|
} // Bus
|
TbtProgramLtr ((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunction, (UINT8) mTbtNvsAreaPtr->TbtLtr);
|
}
|
|
/*
|
US ports and endpoints which declare support must also have the LTR capability structure (cap ID 18h).
|
In this structure you need to enter the max snoop latency and max non-snoop latency in accordance with the format specified in the PCIe spec.
|
The latency value itself is platform specific so you'll need to get it from the platform architect or whatever.
|
*/
|
VOID
|
ThunderboltGetLatencyLtr (
|
VOID
|
)
|
{
|
PCH_SERIES PchSeries;
|
|
PchSeries = GetPchSeries ();
|
|
if(gCurrentDiscreteTbtRootPortType == DTBT_TYPE_PEG) {
|
// PEG selector
|
TbtLtrMaxSnoopLatency = LTR_MAX_SNOOP_LATENCY_VALUE;
|
TbtLtrMaxNoSnoopLatency = LTR_MAX_NON_SNOOP_LATENCY_VALUE;
|
} else if (gCurrentDiscreteTbtRootPortType == DTBT_TYPE_PCH) {
|
// PCH selector
|
|
if (PchSeries == PchLp) {
|
TbtLtrMaxSnoopLatency = 0x1003;
|
TbtLtrMaxNoSnoopLatency = 0x1003;
|
}
|
if (PchSeries == PchH) {
|
TbtLtrMaxSnoopLatency = 0x0846;
|
TbtLtrMaxNoSnoopLatency = 0x0846;
|
}
|
}
|
}
|
|
VOID
|
SetLatencyLtr (
|
IN UINT8 Bus,
|
IN UINT8 Dev,
|
IN UINT8 Fun,
|
IN UINT16 CapHeaderOffsetExtd,
|
IN UINT16 LtrMaxSnoopLatency,
|
IN UINT16 LtrMaxNoSnoopLatency
|
)
|
{
|
UINT64 DeviceBaseAddress;
|
if(CapHeaderOffsetExtd == 0) {
|
return;
|
}
|
DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
|
PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffsetExtd + 0x004, LtrMaxSnoopLatency);
|
PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffsetExtd + 0x006, LtrMaxNoSnoopLatency);
|
}
|
|
VOID
|
ThunderboltSetLatencyLtr (
|
IN UINTN RpSegment,
|
IN UINTN RpBus,
|
IN UINTN RpDevice,
|
IN UINTN RpFunction
|
)
|
{
|
UINT8 Bus;
|
UINT8 Dev;
|
UINT8 Fun;
|
UINT8 MinBus;
|
UINT8 MaxBus;
|
UINT16 DeviceId;
|
UINT64 DeviceBaseAddress;
|
UINT8 CapHeaderOffsetStd;
|
UINT16 CapHeaderOffsetExtd;
|
UINT16 DevicePortType;
|
|
MinBus = 0;
|
MaxBus = 0;
|
|
MinBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
|
MaxBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
|
DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinBus, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
|
if (!(IsTbtHostRouter (DeviceId))) {
|
return;
|
}
|
|
TbtSegment = (UINT8)RpSegment;
|
|
for (Bus = MinBus; Bus <= MaxBus; ++Bus) {
|
for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
|
for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
|
//
|
// Check for Device availability
|
//
|
DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
|
if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
|
//
|
// Device not present
|
//
|
continue;
|
}
|
|
CapHeaderOffsetStd = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10);
|
DevicePortType = (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffsetStd + 0x002) >> 4) & 0xF;
|
|
CapHeaderOffsetExtd = PcieFindExtendedCapId (Bus, Dev, Fun, 0x0018);
|
|
switch (DevicePortType) {
|
case 0:
|
//
|
// PCI Express Endpoint
|
//
|
SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd, TbtLtrMaxSnoopLatency, TbtLtrMaxNoSnoopLatency);
|
break;
|
|
case 1:
|
//
|
// Legacy PCI Express Endpoint
|
//
|
SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd, TbtLtrMaxSnoopLatency, TbtLtrMaxNoSnoopLatency);
|
break;
|
|
case 4:
|
//
|
// Root Port of PCI Express Root Complex
|
//
|
// Do-nothing
|
break;
|
|
case 5:
|
//
|
// Upstream Port of PCI Express Switch
|
//
|
SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd, TbtLtrMaxSnoopLatency, TbtLtrMaxNoSnoopLatency);
|
break;
|
|
case 6:
|
//
|
// Downstream Port of PCI Express Switch
|
//
|
// Do-nothing
|
break;
|
|
case 7:
|
//
|
// PCI Express to PCI/PCI-X Bridge
|
//
|
// Do-nothing
|
break;
|
|
case 8:
|
//
|
// PCI/PCI-X to PCI Express Bridge
|
//
|
// Do-nothing
|
break;
|
|
case 9:
|
//
|
// Root Complex Integrated Endpoint
|
//
|
// Do-nothing
|
break;
|
|
case 10:
|
//
|
// Root Complex Event Collector
|
//
|
// Do-nothing
|
break;
|
|
default:
|
break;
|
}
|
//
|
// switch(DevicePortType)
|
//
|
}
|
//
|
// Fun
|
//
|
}
|
//
|
// Dev
|
//
|
}
|
//
|
// Bus
|
//
|
}
|
|
static
|
VOID
|
Stall (
|
UINTN Usec
|
)
|
{
|
UINTN Index;
|
UINT32 Data32;
|
UINT32 PrevData;
|
UINTN Counter;
|
|
Counter = (UINTN) ((Usec * 10) / 3);
|
//
|
// Call WaitForTick for Counter + 1 ticks to try to guarantee Counter tick
|
// periods, thus attempting to ensure Microseconds of stall time.
|
//
|
if (Counter != 0) {
|
|
PrevData = IoRead32 (PcdGet16 (PcdAcpiBaseAddress) + R_PCH_ACPI_PM1_TMR);
|
for (Index = 0; Index < Counter;) {
|
Data32 = IoRead32 (PcdGet16 (PcdAcpiBaseAddress) + R_PCH_ACPI_PM1_TMR);
|
if (Data32 < PrevData) {
|
//
|
// Reset if there is a overlap
|
//
|
PrevData = Data32;
|
continue;
|
}
|
|
Index += (Data32 - PrevData);
|
PrevData = Data32;
|
}
|
}
|
|
return ;
|
}
|
/**
|
Called during Sx entry, initates TbtSetPcie2TbtCommand HandShake to set GO2SX_NO_WAKE
|
for Tbt devices if WakeupSupport is not present.
|
|
@param[in] DispatchHandle - The unique handle assigned to this handler by SmiHandlerRegister().
|
@param[in] DispatchContext - Points to an optional handler context which was specified when the
|
handler was registered.
|
@param[in, out] CommBuffer - A pointer to a collection of data in memory that will
|
be conveyed from a non-SMM environment into an SMM environment.
|
@param[in, out] CommBufferSize - The size of the CommBuffer.
|
|
@retval EFI_SUCCESS - The interrupt was handled successfully.
|
**/
|
EFI_STATUS
|
EFIAPI
|
SxDTbtEntryCallback (
|
IN EFI_HANDLE DispatchHandle,
|
IN CONST VOID *DispatchContext,
|
IN OUT VOID *CommBuffer OPTIONAL,
|
IN UINTN *CommBufferSize OPTIONAL
|
)
|
{
|
UINT16 DeviceId;
|
UINT8 CableConnected;
|
UINT8 RootportSelected;
|
UINT8 HoustRouteBus;
|
volatile UINT32 *PowerState;
|
UINT32 PowerStatePrev;
|
BOOLEAN SecSubBusAssigned;
|
UINT64 DeviceBaseAddress;
|
UINT8 CapHeaderOffset;
|
UINTN RpDev;
|
UINTN RpFunc;
|
EFI_STATUS Status;
|
UINT32 Timeout;
|
UINT32 RegisterValue;
|
UINT64 Tbt2Pcie;
|
UINTN Index;
|
UINT32 TbtCioPlugEventGpioNo;
|
UINT32 TbtFrcPwrGpioNo;
|
UINT8 TbtFrcPwrGpioLevel;
|
UINT32 TbtPcieRstGpioNo;
|
UINT8 TbtPcieRstGpioLevel;
|
EFI_SMM_SX_REGISTER_CONTEXT *EntryDispatchContext;
|
|
CableConnected = 0;
|
HoustRouteBus = 3;
|
SecSubBusAssigned = FALSE;
|
Timeout = 600;
|
RootportSelected = 0;
|
TbtCioPlugEventGpioNo = 0;
|
TbtFrcPwrGpioNo = 0;
|
TbtFrcPwrGpioLevel = 0;
|
TbtPcieRstGpioNo = 0;
|
TbtPcieRstGpioLevel = 0;
|
Index = 0;
|
|
EntryDispatchContext = (EFI_SMM_SX_REGISTER_CONTEXT*) DispatchContext;
|
|
// CableConnected = GetTbtHostRouterStatus ();
|
//SaveTbtHostRouterStatus (CableConnected & 0xF0);
|
//
|
// Get the Power State and Save
|
//
|
if (((mTbtNvsAreaPtr->DTbtControllerEn0 == 0) && (Index == 0))) {
|
|
RootportSelected = mTbtNvsAreaPtr->RootportSelected0;
|
TbtCioPlugEventGpioNo = mTbtNvsAreaPtr->TbtCioPlugEventGpioNo0;
|
TbtFrcPwrGpioNo = mTbtNvsAreaPtr->TbtFrcPwrGpioNo0;
|
TbtFrcPwrGpioLevel = mTbtNvsAreaPtr->TbtFrcPwrGpioLevel0;
|
TbtPcieRstGpioNo = mTbtNvsAreaPtr->TbtPcieRstGpioNo0;
|
TbtPcieRstGpioLevel = mTbtNvsAreaPtr->TbtPcieRstGpioLevel0;
|
}
|
|
Status = GetDTbtRpDevFun (gCurrentDiscreteTbtRootPortType, RootportSelected - 1, &RpDev, &RpFunc);
|
ASSERT_EFI_ERROR (Status);
|
CapHeaderOffset = PcieFindCapId (TbtSegment, 0x00, (UINT8)RpDev, (UINT8)RpFunc, 0x01);
|
DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, 0x00, (UINT32)RpDev, (UINT32)RpFunc, 0);
|
PowerState = &*((volatile UINT32 *) (mPciExpressBaseAddress + DeviceBaseAddress + CapHeaderOffset + 4)); //PMCSR
|
PowerStatePrev = *PowerState;
|
*PowerState &= 0xFFFFFFFC;
|
|
HoustRouteBus = PciSegmentRead8 (DeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
|
//
|
// Check the Subordinate bus .If it is Zero ,assign temporary bus to
|
// find the device presence .
|
//
|
if (HoustRouteBus == 0) {
|
PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 0xF0);
|
PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, 0xF0);
|
HoustRouteBus = 0xF0;
|
SecSubBusAssigned = TRUE;
|
}
|
//
|
// Clear Interrupt capability of TBT CIO Plug Event Pin to make sure no SCI is getting generated,
|
// This GPIO will be reprogrammed while resuming as part of Platform GPIO Programming.
|
//
|
GpioSetPadInterruptConfig (TbtCioPlugEventGpioNo, GpioIntDis);
|
//
|
// Read the TBT Host router DeviceID
|
//
|
DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (TbtSegment, HoustRouteBus, 0, 0, PCI_DEVICE_ID_OFFSET));
|
|
//
|
// Check For HostRouter Presence
|
//
|
if (IsTbtHostRouter (DeviceId)) {
|
// CableConnected = GetTbtHostRouterStatus ();
|
if (!((CableConnected & (DTBT_SAVE_STATE_OFFSET << Index)) == (DTBT_SAVE_STATE_OFFSET << Index))) {
|
CableConnected = CableConnected | (DTBT_SAVE_STATE_OFFSET << Index);
|
// SaveTbtHostRouterStatus (CableConnected);
|
}
|
}
|
|
//
|
// Check value of Tbt2Pcie reg, if Tbt is not present, bios needs to apply force power prior to sending mailbox command
|
//
|
GET_TBT2PCIE_REGISTER_ADDRESS(TbtSegment, HoustRouteBus, 0x00, 0x00, Tbt2Pcie)
|
RegisterValue = PciSegmentRead32 (Tbt2Pcie);
|
if (0xFFFFFFFF == RegisterValue) {
|
|
GpioWrite (TbtFrcPwrGpioNo,TbtFrcPwrGpioLevel);
|
|
while (Timeout -- > 0) {
|
RegisterValue = PciSegmentRead32 (Tbt2Pcie);
|
if (0xFFFFFFFF != RegisterValue) {
|
break;
|
}
|
Stall(1* (UINTN)1000);
|
}
|
//
|
// Before entering Sx state BIOS should execute GO2SX/NO_WAKE mailbox command for AIC.
|
// However BIOS shall not execute go2sx mailbox command on S5/reboot cycle.
|
//
|
|
if( (EntryDispatchContext->Type == SxS3) || (EntryDispatchContext->Type == SxS4))
|
{
|
if(!mTbtNvsAreaPtr->TbtWakeupSupport) {
|
//Wake Disabled, GO2SX_NO_WAKE Command
|
TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX_NO_WAKE, HoustRouteBus, 0, 0, TBT_5S_TIMEOUT);
|
} else {
|
//Wake Enabled, GO2SX Command
|
TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX, HoustRouteBus, 0, 0, TBT_5S_TIMEOUT);
|
}
|
}
|
if (mTbtNvsAreaPtr->TbtFrcPwrEn == 0) {
|
GpioWrite (TbtFrcPwrGpioNo,!(TbtFrcPwrGpioLevel));
|
}
|
} else {
|
//
|
// Before entering Sx state BIOS should execute GO2SX/NO_WAKE mailbox command for AIC.
|
// However BIOS shall not execute go2sx mailbox command on S5/reboot cycle.
|
//
|
if( (EntryDispatchContext->Type == SxS3) || (EntryDispatchContext->Type == SxS4))
|
{
|
if(!mTbtNvsAreaPtr->TbtWakeupSupport) {
|
//Wake Disabled, GO2SX_NO_WAKE Command
|
TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX_NO_WAKE, HoustRouteBus, 0, 0, TBT_5S_TIMEOUT);
|
} else {
|
//Wake Enabled, GO2SX Command
|
TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX, HoustRouteBus, 0, 0, TBT_5S_TIMEOUT);
|
}
|
}
|
}
|
*PowerState = PowerStatePrev;
|
//
|
// Restore the bus number in case we assigned temporarily
|
//
|
if (SecSubBusAssigned) {
|
PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 0x00);
|
PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, 0x00);
|
}
|
if (gDTbtPcieRstSupport) {
|
GpioWrite (TbtPcieRstGpioNo,TbtPcieRstGpioLevel);
|
}
|
return EFI_SUCCESS;
|
}
|
|
VOID
|
ThunderboltSwSmiCallback (
|
IN UINT8 Type
|
)
|
{
|
UINT8 ThunderboltSmiFunction;
|
|
DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback Entry\n"));
|
ThunderboltSmiFunction = mTbtNvsAreaPtr->ThunderboltSmiFunction;
|
DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback. ThunderboltSmiFunction=%d\n", ThunderboltSmiFunction));
|
if (Type == DTBT_CONTROLLER) {
|
gCurrentDiscreteTbtRootPort = mTbtNvsAreaPtr->CurrentDiscreteTbtRootPort;
|
gCurrentDiscreteTbtRootPortType = mTbtNvsAreaPtr->CurrentDiscreteTbtRootPortType;
|
}
|
|
switch (ThunderboltSmiFunction) {
|
case 21:
|
ThunderboltCallback (Type);
|
break;
|
|
case 22:
|
TbtDisablePCIDevicesAndBridges (Type);
|
break;
|
|
case 23:
|
ConfigureTbtAspm (Type, (UINT16) 0x02);
|
break;
|
|
case 24:
|
ConfigureTbtAspm (Type, (UINT16) 0x01);
|
break;
|
|
default:
|
break;
|
}
|
DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback Exit.\n"));
|
}
|
STATIC
|
EFI_STATUS
|
EFIAPI
|
DiscreteThunderboltSwSmiCallback (
|
IN EFI_HANDLE DispatchHandle,
|
IN CONST VOID *DispatchContext,
|
IN OUT VOID *CommBuffer OPTIONAL,
|
IN UINTN *CommBufferSize OPTIONAL
|
)
|
{
|
ThunderboltSwSmiCallback(DTBT_CONTROLLER);
|
return EFI_SUCCESS;
|
}
|
EFI_STATUS
|
TbtRegisterHandlers (
|
IN BOOLEAN Type
|
)
|
{
|
EFI_STATUS Status;
|
UINTN SmiInputValue;
|
EFI_SMM_HANDLER_ENTRY_POINT2 SxHandler;
|
EFI_SMM_HANDLER_ENTRY_POINT2 SwHandler;
|
EFI_SMM_SX_DISPATCH2_PROTOCOL *SxDispatchProtocol;
|
EFI_SMM_SW_DISPATCH2_PROTOCOL *SwDispatch;
|
EFI_SMM_SX_REGISTER_CONTEXT EntryDispatchContext;
|
EFI_SMM_SW_REGISTER_CONTEXT SwContext;
|
EFI_HANDLE SwDispatchHandle;
|
EFI_HANDLE S3DispatchHandle;
|
EFI_HANDLE S4DispatchHandle;
|
EFI_HANDLE S5DispatchHandle;
|
|
Status = EFI_UNSUPPORTED;
|
|
if(Type == DTBT_CONTROLLER) {
|
SxHandler = SxDTbtEntryCallback;
|
SwHandler = DiscreteThunderboltSwSmiCallback;
|
SmiInputValue = PcdGet8 (PcdSwSmiDTbtEnumerate);
|
gDTbtPcieRstSupport = gTbtInfoHob->DTbtCommonConfig.PcieRstSupport;
|
Status = EFI_SUCCESS;
|
}
|
if (EFI_ERROR (Status)) {
|
return Status;
|
}
|
|
SwDispatchHandle = NULL;
|
S3DispatchHandle = NULL;
|
S4DispatchHandle = NULL;
|
S5DispatchHandle = NULL;
|
|
Status = gSmst->SmmLocateProtocol (
|
&gEfiSmmSxDispatch2ProtocolGuid,
|
NULL,
|
(VOID **) &SxDispatchProtocol
|
);
|
ASSERT_EFI_ERROR (Status);
|
//
|
// Register S3 entry phase call back function
|
//
|
EntryDispatchContext.Type = SxS3;
|
EntryDispatchContext.Phase = SxEntry;
|
Status = SxDispatchProtocol->Register (
|
SxDispatchProtocol,
|
SxHandler,
|
&EntryDispatchContext,
|
&S3DispatchHandle
|
);
|
ASSERT_EFI_ERROR (Status);
|
//
|
// Register S4 entry phase call back function
|
//
|
EntryDispatchContext.Type = SxS4;
|
EntryDispatchContext.Phase = SxEntry;
|
Status = SxDispatchProtocol->Register (
|
SxDispatchProtocol,
|
SxHandler,
|
&EntryDispatchContext,
|
&S4DispatchHandle
|
);
|
ASSERT_EFI_ERROR (Status);
|
//
|
// Register S5 entry phase call back function
|
//
|
EntryDispatchContext.Type = SxS5;
|
EntryDispatchContext.Phase = SxEntry;
|
Status = SxDispatchProtocol->Register (
|
SxDispatchProtocol,
|
SxHandler,
|
&EntryDispatchContext,
|
&S5DispatchHandle
|
);
|
ASSERT_EFI_ERROR (Status);
|
//
|
// Locate the SMM SW dispatch protocol
|
//
|
Status = gSmst->SmmLocateProtocol (
|
&gEfiSmmSwDispatch2ProtocolGuid,
|
NULL,
|
(VOID **) &SwDispatch
|
);
|
|
ASSERT_EFI_ERROR (Status);
|
//
|
// Register SWSMI handler
|
//
|
SwContext.SwSmiInputValue = SmiInputValue;
|
Status = SwDispatch->Register (
|
SwDispatch,
|
SwHandler,
|
&SwContext,
|
&SwDispatchHandle
|
);
|
ASSERT_EFI_ERROR (Status);
|
|
return Status;
|
}
|
EFI_STATUS
|
InSmmFunction (
|
IN EFI_HANDLE ImageHandle,
|
IN EFI_SYSTEM_TABLE *SystemTable
|
)
|
{
|
EFI_STATUS Status;
|
|
Status = EFI_SUCCESS;
|
|
Status = TbtRegisterHandlers(DTBT_CONTROLLER);
|
return Status;
|
}
|
|
EFI_STATUS
|
EFIAPI
|
TbtSmmEntryPoint (
|
IN EFI_HANDLE ImageHandle,
|
IN EFI_SYSTEM_TABLE *SystemTable
|
)
|
{
|
TBT_NVS_AREA_PROTOCOL *TbtNvsAreaProtocol;
|
EFI_STATUS Status;
|
|
DEBUG ((DEBUG_INFO, "TbtSmmEntryPoint\n"));
|
|
mPciExpressBaseAddress = PcdGet64 (PcdPciExpressBaseAddress);
|
//
|
// Locate Tbt shared data area
|
//
|
Status = gBS->LocateProtocol (&gTbtNvsAreaProtocolGuid, NULL, (VOID **) &TbtNvsAreaProtocol);
|
ASSERT_EFI_ERROR (Status);
|
mTbtNvsAreaPtr = TbtNvsAreaProtocol->Area;
|
|
//
|
// Get TBT INFO HOB
|
//
|
gTbtInfoHob = (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid);
|
if (gTbtInfoHob == NULL) {
|
return EFI_NOT_FOUND;
|
}
|
|
return InSmmFunction (ImageHandle, SystemTable);
|
}
|
|
VOID
|
EndOfThunderboltCallback (
|
IN UINTN RpSegment,
|
IN UINTN RpBus,
|
IN UINTN RpDevice,
|
IN UINTN RpFunction
|
)
|
{
|
if(mTbtNvsAreaPtr->TbtL1SubStates != 0) {
|
ThunderboltEnableL1Sub (mTbtNvsAreaPtr->TbtL1SubStates, RpSegment, RpBus, RpDevice, RpFunction);
|
}
|
ConfigureTbtPm(RpSegment, RpBus, RpDevice, RpFunction, 1);
|
if (!mTbtNvsAreaPtr->TbtAspm) { //Aspm disable case
|
ThunderboltDisableAspmWithoutLtr (RpSegment, RpBus, RpDevice, RpFunction);
|
} else { //Aspm enable case
|
ThunderboltEnableAspmWithoutLtr ((UINT16)mTbtNvsAreaPtr->TbtAspm, RpSegment, RpBus, RpDevice, RpFunction);
|
}
|
|
if (mTbtNvsAreaPtr->TbtLtr) {
|
ThunderboltGetLatencyLtr ();
|
ThunderboltSetLatencyLtr (RpSegment, RpBus, RpDevice, RpFunction);
|
}
|
ConfigureLtr (RpSegment, RpBus, RpDevice, RpFunction);
|
ConfigureTbtPm(RpSegment, RpBus, RpDevice, RpFunction, 2);
|
} // EndOfThunderboltCallback
|
|
VOID
|
ConfigureTbtAspm (
|
IN UINT8 Type,
|
IN UINT16 Aspm
|
)
|
{
|
UINTN RpSegment = 0;
|
UINTN RpBus = 0;
|
UINTN RpDevice;
|
UINTN RpFunction;
|
|
if(Type == DTBT_CONTROLLER) {
|
if (gCurrentDiscreteTbtRootPort == 0) {
|
return;
|
}
|
GetDTbtRpDevFun(DTBT_CONTROLLER, gCurrentDiscreteTbtRootPort - 1, &RpDevice, &RpFunction);
|
|
ConfigureTbtPm (RpSegment, RpBus, RpDevice, RpFunction, 1);
|
if (!mTbtNvsAreaPtr->TbtAspm) { //Aspm disable case
|
ThunderboltDisableAspmWithoutLtr (RpSegment, RpBus, RpDevice, RpFunction);
|
} else { //Aspm enable case
|
ThunderboltEnableAspmWithoutLtr ((UINT16) Aspm, RpSegment, RpBus, RpDevice, RpFunction);
|
}
|
|
if (mTbtNvsAreaPtr->TbtLtr) {
|
ThunderboltGetLatencyLtr ();
|
ThunderboltSetLatencyLtr (RpSegment, RpBus, RpDevice, RpFunction);
|
}
|
ConfigureLtr (RpSegment, RpBus, RpDevice, RpFunction);
|
} // EndOfThunderboltCallback
|
}
|
|
