/** @file
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PeiTbtInit library implementition with empty functions.
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/DebugLib.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/PchPcieRpLib.h>
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#include <Library/TbtCommonLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/TimerLib.h>
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#include <Library/BaseLib.h>
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#include <Library/GpioLib.h>
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/**
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Selects the proper TBT Root port to assign resources
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based on the user input value
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@param[in] SetupData Pointer to Setup data
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@retval TbtSelectorChosen Rootport number.
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**/
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VOID
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GetRootporttoSetResourcesforTbt (
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IN UINTN RpIndex,
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OUT UINT8 *RsvdExtraBusNum,
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OUT UINT16 *RsvdPcieMegaMem,
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OUT UINT8 *PcieMemAddrRngMax,
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OUT UINT16 *RsvdPciePMegaMem,
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OUT UINT8 *PciePMemAddrRngMax,
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OUT BOOLEAN *SetResourceforTbt
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)
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{
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UINTN TbtRpNumber;
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TbtRpNumber = (UINTN) PcdGet8 (PcdDTbtPcieRpNumber);
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if (RpIndex == (TbtRpNumber - 1)) {
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*RsvdExtraBusNum = PcdGet8 (PcdDTbtPcieExtraBusRsvd);
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*RsvdPcieMegaMem = PcdGet16 (PcdDTbtPcieMemRsvd);
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*PcieMemAddrRngMax = PcdGet8 (PcdDTbtPcieMemAddrRngMax);
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*RsvdPciePMegaMem = PcdGet16 (PcdDTbtPciePMemRsvd);
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*PciePMemAddrRngMax = PcdGet8 (PcdDTbtPciePMemAddrRngMax);
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*SetResourceforTbt = TRUE;
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}
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else {
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*SetResourceforTbt = FALSE;
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}
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}
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/**
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Internal function to Wait for Tbt2PcieDone Bit.to Set or clear
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@param[in] CommandOffsetAddress Tbt2Pcie Register Address
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@param[in] TimeOut Time out with 100 ms garnularity
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@param[in] Tbt2PcieDone Wait condition (wait for Bit to Clear/Set)
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@param[out] *Tbt2PcieValue Function Register value
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**/
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BOOLEAN
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InternalWaitforCommandCompletion(
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IN UINT64 CommandOffsetAddress,
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IN UINT32 TimeOut,
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IN BOOLEAN Tbt2PcieDone,
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OUT UINT32 *Tbt2PcieValue
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)
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{
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BOOLEAN ReturnFlag;
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UINT32 Tbt2PcieCheck;
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ReturnFlag = FALSE;
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while (TimeOut-- > 0) {
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*Tbt2PcieValue = PciSegmentRead32 (CommandOffsetAddress);
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if (0xFFFFFFFF == *Tbt2PcieValue ) {
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//
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// Device is not here return now
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//
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ReturnFlag = FALSE;
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break;
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}
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if(Tbt2PcieDone) {
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Tbt2PcieCheck = *Tbt2PcieValue & TBT2PCIE_DON_R;
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} else {
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Tbt2PcieCheck = !(*Tbt2PcieValue & TBT2PCIE_DON_R);
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}
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if (Tbt2PcieCheck) {
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ReturnFlag = TRUE;
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break;
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}
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MicroSecondDelay(TBT_MAIL_BOX_DELAY);
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}
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return ReturnFlag;
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}
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/**
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Get Security Level.
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@param[in] Bus Bus number Host Router (DTBT)
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@param[in] Device Device number for Host Router (DTBT)
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@param[in] Function Function number for Host Router (DTBT)
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@param[in] Command Command for Host Router (DTBT)
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@param[in] Timeout Time out with 100 ms garnularity
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**/
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UINT8
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GetSecLevel (
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Function,
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IN UINT8 Command,
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IN UINT32 Timeout
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)
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{
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UINT64 Pcie2Tbt;
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UINT64 Tbt2Pcie;
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UINT32 RegisterValue;
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UINT8 ReturnFlag;
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ReturnFlag = 0xFF;
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DEBUG ((DEBUG_INFO, "GetSecLevel() \n"));
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GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
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GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
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PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B);
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if(InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE, &RegisterValue)) {
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ReturnFlag = (UINT8) (0xFF & (RegisterValue >> 8));
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}
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PciSegmentWrite32 (Pcie2Tbt, 0);
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InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, FALSE, &RegisterValue);
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DEBUG ((DEBUG_INFO, "Security Level configured to %x \n", ReturnFlag));
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return ReturnFlag;
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}
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/**
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Set Security Level.
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@param[in] Data Security State
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@param[in] Bus Bus number for Host Router (DTBT)
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@param[in] Device Device number for Host Router (DTBT)
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@param[in] Function Function number for Host Router (DTBT)
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@param[in] Command Command for Host Router (DTBT)
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@param[in] Timeout Time out with 100 ms garnularity
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**/
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BOOLEAN
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SetSecLevel (
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IN UINT8 Data,
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Function,
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IN UINT8 Command,
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IN UINT32 Timeout
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)
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{
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UINT64 Pcie2Tbt;
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UINT64 Tbt2Pcie;
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UINT32 RegisterValue;
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BOOLEAN ReturnFlag;
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ReturnFlag = FALSE;
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DEBUG ((DEBUG_INFO, "SetSecLevel() \n"));
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GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
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GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
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PciSegmentWrite32 (Pcie2Tbt, (Data << 8) | Command | PCIE2TBT_VLD_B);
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ReturnFlag = InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE, &RegisterValue);
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DEBUG ((DEBUG_INFO, "RegisterValue %x \n", RegisterValue));
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PciSegmentWrite32 (Pcie2Tbt, 0);
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InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, FALSE, &RegisterValue);
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DEBUG ((DEBUG_INFO, "Return value %x \n", ReturnFlag));
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return ReturnFlag;
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}
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/**
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Based on the Security Mode Selection, BIOS drives FORCE_PWR.
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@param[in] GpioNumber
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@param[in] Value
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**/
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VOID
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ForceDtbtPower(
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IN UINT8 GpioAccessType,
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IN UINT8 Expander,
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IN UINT32 GpioNumber,
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IN BOOLEAN Value
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)
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{
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if (GpioAccessType == 0x01) {
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// PCH
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GpioSetOutputValue (GpioNumber, (UINT32)Value);
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} else if (GpioAccessType == 0x02) {
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// IoExpander {TCA6424A}
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GpioExpSetOutput (Expander, (UINT8)GpioNumber, (UINT8)Value);
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}
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}
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/**
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Execute TBT Mail Box Command
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@param[in] Command TBT Command
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@param[in] Bus Bus number for Host Router (DTBT)
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@param[in] Device Device number for Host Router (DTBT)
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@param[in] Function Function number for Host Router (DTBT)
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@param[in] Timeout Time out with 100 ms garnularity
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@Retval true if command executes succesfully
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**/
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BOOLEAN
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TbtSetPcie2TbtCommand(
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IN UINT8 Command,
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Function,
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IN UINT32 Timeout
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)
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{
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UINT64 Pcie2Tbt;
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UINT64 Tbt2Pcie;
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UINT32 RegisterValue;
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BOOLEAN ReturnFlag;
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GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
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GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
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PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B);
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ReturnFlag = InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE, &RegisterValue);
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PciSegmentWrite32(Pcie2Tbt, 0);
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return ReturnFlag;
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}
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/**
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Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root Port physical Number
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@param[in] RpNumber Root port physical number. (0-based)
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@param[out] RpDev Return corresponding root port device number.
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@param[out] RpFun Return corresponding root port function number.
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@retval EFI_SUCCESS Root port device and function is retrieved
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@retval EFI_INVALID_PARAMETER If Invalid Root Port Number or TYPE is Passed
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**/
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EFI_STATUS
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EFIAPI
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GetDTbtRpDevFun (
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IN BOOLEAN Type,
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IN UINTN RpNumber,
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OUT UINTN *RpDev,
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OUT UINTN *RpFunc
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)
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{
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EFI_STATUS Status;
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UINTN TbtRpDev;
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UINTN TbtRpFunc;
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Status = EFI_INVALID_PARAMETER; // Update the Status to EFI_SUCCESS if valid input found.
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//
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// PCH-H can support up to 24 root ports. PEG0,PEG1 and PEG2 will be
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// with device number 0x1 and Function number 0,1 and 2 respectively.
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//
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if (Type == DTBT_TYPE_PEG)
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{
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//
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// PEG Rootport
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//
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if (RpNumber <= 2) {
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*RpDev = 0x01;
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*RpFunc = RpNumber;
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Status = EFI_SUCCESS;
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}
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}
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if (Type == DTBT_TYPE_PCH)
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{
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//
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// PCH Rootport
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//
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if (RpNumber <= 23) {
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Status = GetPchPcieRpDevFun (RpNumber, &TbtRpDev, &TbtRpFunc);
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*RpDev = TbtRpDev;
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*RpFunc = TbtRpFunc;
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}
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}
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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BOOLEAN
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IsTbtHostRouter (
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IN UINT16 DeviceID
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)
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{
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switch (DeviceID) {
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case AR_HR_2C:
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case AR_HR_4C:
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case AR_HR_LP:
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case AR_HR_C0_2C:
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case AR_HR_C0_4C:
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case TR_HR_2C:
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case TR_HR_4C:
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return TRUE;
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}
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return FALSE;
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} // IsTbtHostRouter
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