/** @file
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TBT Policy Common definition.
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _TBT_POLICY_COMMON_H_
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#define _TBT_POLICY_COMMON_H_
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#include <Library/GpioLib.h>
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#include <IndustryStandard/Pci22.h>
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#define MAX_DTBT_CONTROLLER_NUMBER 2
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#define TYPE_PCIE 0x01
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#define TYPE_PEG 0x02
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#pragma pack(push, 1)
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//
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// dTBT Force Power GPIO Data Structure
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//
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typedef struct _DTBT_FORCE_POWER_GPIO_CONFIG {
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GPIO_PAD GpioPad; ///< GPIO Pad Number
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BOOLEAN GpioLevel; ///< 0 = Active Low; 1 = Active High
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UINT8 Reserved[3]; ///< Reserved for DWORD alignment
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} DTBT_FORCE_POWER_GPIO_CONFIG;
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//
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// dTBT CIO Plug Event GPIO Data Structure
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//
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typedef struct _DTBT_CIO_PLUG_EVENT_GPIO_CONFIG {
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GPIO_PAD GpioPad; ///< GPIO Pad Number
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UINT32 AcpiGpeSignature; ///< AcpiPlatform driver will change the XTBT method to the _Lxx or _Exx that we assign in this item.
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BOOLEAN AcpiGpeSignaturePorting; ///< 0 = No porting required(for 2-tier GPI GPE event architecture), 1 = Porting required(for 1-tier GPI GPE event architecture)
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UINT8 Reserved[3]; ///< Reserved for DWORD alignment
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} DTBT_CIO_PLUG_EVENT_GPIO_CONFIG;
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//
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// dTBT PCIE Reset GPIO Data Structure
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//
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typedef struct _DTBT_PCIE_RESET_GPIO_CONFIG {
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GPIO_PAD GpioPad; ///< GPIO Pad Number
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BOOLEAN GpioLevel; ///< 0 = Active Low; 1 = Active High
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UINT8 Reserved[3]; ///< Reserved for DWORD alignment
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} DTBT_PCIE_RESET_GPIO_CONFIG;
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//
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// dTBT Controller Data Structure
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//
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typedef struct _DTBT_CONTROLLER_CONFIG {
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UINT8 DTbtControllerEn; ///< Enable/Disable DTbtController.
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UINT8 Type; ///< 01-Pcie RP, 02- PEG,Reserved. <Specific according to Board Design>
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UINT8 PcieRpNumber; ///< RP Number/ PEG Port (0,1,2) that connecet to dTBT controller. <Specific according to Board Design>
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DTBT_FORCE_POWER_GPIO_CONFIG ForcePwrGpio; ///< The GPIO pin that can force dTBT Power On. <Specific according to Board Design>
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DTBT_CIO_PLUG_EVENT_GPIO_CONFIG CioPlugEventGpio; ///< The GPIO pin that can generate Hot-Plug event. <Specific according to Board Design>
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DTBT_PCIE_RESET_GPIO_CONFIG PcieRstGpio; ///< The GPIO pin that is use to perform Reset when platform enters to Sx, it is required for platforms where PCI_RST pin connected to Tbt is controlled with GPIO <Specific according to Board Design>
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GPIO_PAD PdResetGpioPad; ///< PD HRESET GPIO Pad Number
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GPIO_PAD PdSxEntryGpioPad; ///< PD SX Entry GPIO Pad Number
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GPIO_PAD PdSxAckGpioPad; ///< PD SX Ack GPIO Pad Number
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UINT8 Reserved[1]; ///< Reserved for DWORD alignment
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} DTBT_CONTROLLER_CONFIG;
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//
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// dTBT Controller Data Structure
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//
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typedef struct _DTBT_COMMON_CONFIG {
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UINT8 TbtBootOn; ///< Send BootOn Mailbox command when TbtBootOn is enabled.
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UINT8 TbtUsbOn; ///< Send UsbOn Mailbox command when TbtBootOn is enabled.
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UINT8 Gpio3ForcePwr; ///< Force GPIO to power on or not
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UINT16 Gpio3ForcePwrDly; ///< The delay time after do ForcePwr
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BOOLEAN DTbtSharedGpioConfiguration; ///< Multiple DTBT controllers share the same GPIO pin <Specific according to Board Design>
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BOOLEAN PcieRstSupport; ///< 0 = Not Support, 1 = Supported. it is required for platforms where PCI_RST pin connected to Tbt is controlled with GPIO
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UINT8 SecurityMode; ///< 0: SL0 No Security, 1: SL1 User Authorization, 2: SL2 Secure Connect, 3: SL3 Display Port and USB
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UINT8 ControlIommu; ///< Control Iommu behavior in pre-boot, 0: Disabled Iommu, 1: Enable Iommu, Disable exception list, 2: Enable Iommu, Enable exception list
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UINT8 Reserved[3]; ///< Reserved for DWORD alignment
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} DTBT_COMMON_CONFIG;
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#pragma pack(pop)
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#endif
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