/** @file
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TBT DXE Policy
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _DXE_TBT_POLICY_H_
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#define _DXE_TBT_POLICY_H_
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#include <TbtPolicyCommonDefinition.h>
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#pragma pack(push, 1)
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#define DXE_TBT_POLICY_REVISION 1
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//
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// TBT Common Data Structure
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//
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typedef struct _TBT_COMMON_CONFIG{
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/**
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TBT Security Level
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<b>0: SL0 No Security</b>, 1: SL1 User Authorization, 2: SL2 Secure Connect, 3: SL3 Display Port and USB
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**/
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UINT32 SecurityMode : 3;
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/**
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BIOS W/A for Hot plug of 12V USB devices cause electrical noise on PCH GPIOs
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<b>0: Disabled</b>, 1: Enabled
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**/
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UINT32 Gpio5Filter : 1;
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/**
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WA for TR A0 OS_UP Command, it is only needed for TR A0 stepping
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<b>0: Disabled</b>, 1: Enabled
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**/
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UINT32 TrA0OsupWa : 1;
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/**
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Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport
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<b>0: Disabled</b>, 1: Enabled
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**/
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UINT32 TbtWakeupSupport : 1;
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/**
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SMI TBT enumeration
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<b>0: Disabled</b>, 1: Enabled
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**/
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UINT32 TbtHotSMI : 1;
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/**
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Notify PCIe RP after Hot-Plug/Hot-Unplug occurred.
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<b>0: Disabled</b>, 1: Enabled
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**/
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UINT32 TbtHotNotify : 1;
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/**
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CLK REQ for all the PCIe device in TBT daisy chain.
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<b>0: Disabled</b>, 1: Enabled
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**/
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UINT32 TbtSetClkReq : 1;
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/**
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ASPM setting for all the PCIe device in TBT daisy chain.
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<b>0: Disabled</b>, 1: L0s, 2: L1, 3: L0sL1
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**/
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UINT32 TbtAspm : 2;
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/**
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L1 SubState for for all the PCIe device in TBT daisy chain.
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<b>0: Disabled</b>, 1: L1.1, 2: L1.1 & L1.2
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**/
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UINT32 TbtL1SubStates : 2;
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/**
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LTR for for all the PCIe device in TBT daisy chain.
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<b>0: Disabled</b>, 1: Enabled
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**/
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UINT32 TbtLtr : 1;
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/**
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PTM for for all the PCIe device in TBT daisy chain.
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<b>0: Disabled</b>, 1: Enabled
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**/
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UINT32 TbtPtm : 1;
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/**
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TBT Dynamic AC/DC L1.
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<b>0: Disabled</b>, 1: Enabled
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**/
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UINT32 TbtAcDcSwitch : 1;
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/**
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TBT RTD3 Support.
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<b>0: Disabled</b>, 1: Enabled
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**/
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UINT32 Rtd3Tbt : 1;
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/**
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TBT ClkReq for RTD3 Flow.
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<b>0: Disabled</b>, 1: Enabled
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**/
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UINT32 Rtd3TbtClkReq : 1;
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/**
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TBT Win10support for Tbt FW execution mode.
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<b>0: Disabled</b>, 1: Native, 2: Native + RTD3
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**/
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UINT32 Win10Support : 2;
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/**
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TbtVtdBaseSecurity
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<b>0: Disabled</b>, 1: Enabled
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**/
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UINT32 TbtVtdBaseSecurity: 1;
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/**
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Control Iommu behavior in pre-boot
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<b>0: Disabled Iommu</b>, 1: Enable Iommu, Disable exception list, 2: Enable Iommu, Enable exception list
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**/
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UINT32 ControlIommu : 3;
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UINT32 Rsvd0 : 8; ///< Reserved bits
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UINT16 Rtd3TbtClkReqDelay;
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UINT16 Rtd3TbtOffDelay;
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} TBT_COMMON_CONFIG;
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//
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// dTBT Resource Data Structure
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//
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typedef struct _DTBT_RESOURCE_CONFIG{
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UINT8 DTbtPcieExtraBusRsvd; ///< Preserve Bus resource for PCIe RP that connect to dTBT Host Router
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UINT16 DTbtPcieMemRsvd; ///< Preserve MEM resource for PCIe RP that connect to dTBT Host Router
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UINT8 DTbtPcieMemAddrRngMax; ///< Alignment of Preserve MEM resource for PCIe RP that connect to dTBT Host Router
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UINT16 DTbtPciePMemRsvd; ///< Preserve PMEM resource for PCIe RP that connect to dTBT Host Router
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UINT8 DTbtPciePMemAddrRngMax; ///< Alignment of Preserve PMEM resource for PCIe RP that connect to dTBT Host Router
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UINT8 Reserved[1]; ///< Reserved for DWORD alignment
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} DTBT_RESOURCE_CONFIG;
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/**
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TBT DXE configuration\n
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<b>Revision 1</b>:
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- Initial version.
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**/
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typedef struct _DXE_TBT_POLICY_PROTOCOL {
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TBT_COMMON_CONFIG TbtCommonConfig; ///< Tbt Common Information
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DTBT_RESOURCE_CONFIG DTbtResourceConfig[MAX_DTBT_CONTROLLER_NUMBER]; ///< dTbt Resource Configuration
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} DXE_TBT_POLICY_PROTOCOL;
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#pragma pack(pop)
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#endif
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