/** @file
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Source code for the board PCH configuration Pcd init functions for Pre-Memory Init phase.
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "CometlakeURvpInit.h"
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#include <GpioPinsCnlLp.h>
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#include <GpioPinsCnlH.h>
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#include <PlatformBoardConfig.h> // for USB 20 AFE & Root Port Clk Info.
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#include <Library/BaseMemoryLib.h>
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#include <Library/GpioLib.h>
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/**
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Board Root Port Clock Info configuration init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integrer represent the board id.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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RootPortClkInfoInit (
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IN UINT16 BoardId
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)
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{
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PCD64_BLOB *Clock;
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UINT32 Index;
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Clock = AllocateZeroPool (16 * sizeof (PCD64_BLOB));
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ASSERT (Clock != NULL);
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if (Clock == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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//
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// The default clock assignment will be FREE_RUNNING, which corresponds to PchClockUsageUnspecified
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// This is safe but power-consuming setting. If Platform code doesn't contain port-clock map for a given board,
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// the clocks will keep on running anyway, allowing PCIe devices to operate. Downside is that clocks will
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// continue to draw power. To prevent this, remember to provide port-clock map for every board.
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//
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for (Index = 0; Index < 16; Index++) {
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Clock[Index].PcieClock.ClkReqSupported = TRUE;
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Clock[Index].PcieClock.ClockUsage = FREE_RUNNING;
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}
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///
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/// Assign ClkReq signal to root port. (Base 0)
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/// For LP, Set 0 - 5
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/// For H, Set 0 - 15
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/// Note that if GbE is enabled, ClkReq assigned to GbE will not be available for Root Port.
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///
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switch (BoardId) {
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// CLKREQ
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case BoardIdCometLakeULpddr3Rvp:
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Clock[0].PcieClock.ClockUsage = PCIE_PCH + 1;
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Clock[1].PcieClock.ClockUsage = PCIE_PCH + 8;
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Clock[2].PcieClock.ClockUsage = LAN_CLOCK;
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Clock[3].PcieClock.ClockUsage = PCIE_PCH + 13;
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Clock[4].PcieClock.ClockUsage = PCIE_PCH + 4;
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Clock[5].PcieClock.ClockUsage = PCIE_PCH + 14;
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break;
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default:
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break;
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}
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PcdSet64S (PcdPcieClock0, Clock[ 0].Blob);
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PcdSet64S (PcdPcieClock1, Clock[ 1].Blob);
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PcdSet64S (PcdPcieClock2, Clock[ 2].Blob);
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PcdSet64S (PcdPcieClock3, Clock[ 3].Blob);
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PcdSet64S (PcdPcieClock4, Clock[ 4].Blob);
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PcdSet64S (PcdPcieClock5, Clock[ 5].Blob);
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PcdSet64S (PcdPcieClock6, Clock[ 6].Blob);
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PcdSet64S (PcdPcieClock7, Clock[ 7].Blob);
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PcdSet64S (PcdPcieClock8, Clock[ 8].Blob);
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PcdSet64S (PcdPcieClock9, Clock[ 9].Blob);
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PcdSet64S (PcdPcieClock10, Clock[10].Blob);
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PcdSet64S (PcdPcieClock11, Clock[11].Blob);
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PcdSet64S (PcdPcieClock12, Clock[12].Blob);
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PcdSet64S (PcdPcieClock13, Clock[13].Blob);
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PcdSet64S (PcdPcieClock14, Clock[14].Blob);
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PcdSet64S (PcdPcieClock15, Clock[15].Blob);
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return EFI_SUCCESS;
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}
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/**
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Board USB related configuration init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integrer represent the board id.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
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UsbConfigInit (
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IN UINT16 BoardId
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)
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{
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PCD32_BLOB *UsbPort20Afe;
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UsbPort20Afe = AllocateZeroPool (PCH_MAX_USB2_PORTS * sizeof (PCD32_BLOB));
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ASSERT (UsbPort20Afe != NULL);
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if (UsbPort20Afe == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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//
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// USB2 AFE settings.
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//
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UsbPort20Afe[0].Info.Petxiset = 7;
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UsbPort20Afe[0].Info.Txiset = 5;
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UsbPort20Afe[0].Info.Predeemp = 3;
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UsbPort20Afe[0].Info.Pehalfbit = 0;
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UsbPort20Afe[1].Info.Petxiset = 7;
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UsbPort20Afe[1].Info.Txiset = 5;
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UsbPort20Afe[1].Info.Predeemp = 3;
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UsbPort20Afe[1].Info.Pehalfbit = 0;
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UsbPort20Afe[2].Info.Petxiset = 7;
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UsbPort20Afe[2].Info.Txiset = 5;
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UsbPort20Afe[2].Info.Predeemp = 3;
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UsbPort20Afe[2].Info.Pehalfbit = 0;
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UsbPort20Afe[3].Info.Petxiset = 7;
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UsbPort20Afe[3].Info.Txiset = 5;
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UsbPort20Afe[3].Info.Predeemp = 3;
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UsbPort20Afe[3].Info.Pehalfbit = 0;
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UsbPort20Afe[4].Info.Petxiset = 7;
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UsbPort20Afe[4].Info.Txiset = 5;
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UsbPort20Afe[4].Info.Predeemp = 3;
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UsbPort20Afe[4].Info.Pehalfbit = 0;
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UsbPort20Afe[5].Info.Petxiset = 7;
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UsbPort20Afe[5].Info.Txiset = 5;
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UsbPort20Afe[5].Info.Predeemp = 3;
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UsbPort20Afe[5].Info.Pehalfbit = 0;
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UsbPort20Afe[6].Info.Petxiset = 7;
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UsbPort20Afe[6].Info.Txiset = 5;
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UsbPort20Afe[6].Info.Predeemp = 3;
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UsbPort20Afe[6].Info.Pehalfbit = 0;
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UsbPort20Afe[7].Info.Petxiset = 7;
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UsbPort20Afe[7].Info.Txiset = 5;
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UsbPort20Afe[7].Info.Predeemp = 3;
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UsbPort20Afe[7].Info.Pehalfbit = 0;
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UsbPort20Afe[8].Info.Petxiset = 7;
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UsbPort20Afe[8].Info.Txiset = 5;
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UsbPort20Afe[8].Info.Predeemp = 3;
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UsbPort20Afe[8].Info.Pehalfbit = 0;
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UsbPort20Afe[9].Info.Petxiset = 7;
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UsbPort20Afe[9].Info.Txiset = 5;
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UsbPort20Afe[9].Info.Predeemp = 3;
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UsbPort20Afe[9].Info.Pehalfbit = 0;
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//
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// USB Port Over Current Pin
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//
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PcdSet8S (PcdUsb20OverCurrentPinPort0, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb20OverCurrentPinPort1, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb20OverCurrentPinPort2, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb20OverCurrentPinPort3, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb20OverCurrentPinPort4, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb20OverCurrentPinPort5, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb20OverCurrentPinPort6, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb20OverCurrentPinPort7, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb20OverCurrentPinPort8, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb20OverCurrentPinPort9, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb20OverCurrentPinPort10, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb20OverCurrentPinPort11, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb20OverCurrentPinPort12, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb20OverCurrentPinPort13, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb20OverCurrentPinPort14, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb20OverCurrentPinPort15, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb30OverCurrentPinPort0, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb30OverCurrentPinPort1, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb30OverCurrentPinPort2, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb30OverCurrentPinPort3, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb30OverCurrentPinPort4, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb30OverCurrentPinPort5, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb30OverCurrentPinPort6, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb30OverCurrentPinPort7, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb30OverCurrentPinPort8, UsbOverCurrentPinMax);
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PcdSet8S (PcdUsb30OverCurrentPinPort9, UsbOverCurrentPinMax);
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switch (BoardId) {
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case BoardIdCometLakeULpddr3Rvp:
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PcdSet8S (PcdUsb20OverCurrentPinPort0, UsbOverCurrentPin2);
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PcdSet8S (PcdUsb20OverCurrentPinPort1, UsbOverCurrentPinSkip);
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PcdSet8S (PcdUsb20OverCurrentPinPort2, UsbOverCurrentPin2);
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PcdSet8S (PcdUsb20OverCurrentPinPort3, UsbOverCurrentPin2);
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PcdSet8S (PcdUsb20OverCurrentPinPort4, UsbOverCurrentPin3);
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PcdSet8S (PcdUsb20OverCurrentPinPort5, UsbOverCurrentPin3);
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PcdSet8S (PcdUsb20OverCurrentPinPort6, UsbOverCurrentPin3);
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PcdSet8S (PcdUsb20OverCurrentPinPort7, UsbOverCurrentPin3);
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PcdSet8S (PcdUsb20OverCurrentPinPort8, UsbOverCurrentPinSkip);
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PcdSet8S (PcdUsb20OverCurrentPinPort9, UsbOverCurrentPinSkip);
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PcdSet8S (PcdUsb20OverCurrentPinPort10, UsbOverCurrentPinSkip);
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PcdSet8S (PcdUsb20OverCurrentPinPort11, UsbOverCurrentPinSkip);
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PcdSet8S (PcdUsb20OverCurrentPinPort12, UsbOverCurrentPinSkip);
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PcdSet8S (PcdUsb20OverCurrentPinPort13, UsbOverCurrentPinSkip);
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PcdSet8S (PcdUsb20OverCurrentPinPort14, UsbOverCurrentPinSkip);
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PcdSet8S (PcdUsb20OverCurrentPinPort15, UsbOverCurrentPinSkip);
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PcdSet8S (PcdUsb30OverCurrentPinPort0, UsbOverCurrentPin2);
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PcdSet8S (PcdUsb30OverCurrentPinPort1, UsbOverCurrentPinSkip);
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PcdSet8S (PcdUsb30OverCurrentPinPort2, UsbOverCurrentPin2);
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PcdSet8S (PcdUsb30OverCurrentPinPort3, UsbOverCurrentPin2);
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PcdSet8S (PcdUsb30OverCurrentPinPort4, UsbOverCurrentPinSkip);
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PcdSet8S (PcdUsb30OverCurrentPinPort5, UsbOverCurrentPinSkip);
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PcdSet8S (PcdUsb30OverCurrentPinPort6, UsbOverCurrentPinSkip);
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PcdSet8S (PcdUsb30OverCurrentPinPort7, UsbOverCurrentPinSkip);
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PcdSet8S (PcdUsb30OverCurrentPinPort8, UsbOverCurrentPinSkip);
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PcdSet8S (PcdUsb30OverCurrentPinPort9, UsbOverCurrentPinSkip);
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// USB2.0 AFE settings
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UsbPort20Afe[0].Info.Petxiset = 4;
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UsbPort20Afe[0].Info.Txiset = 0;
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UsbPort20Afe[0].Info.Predeemp = 3;
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UsbPort20Afe[0].Info.Pehalfbit = 0;
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UsbPort20Afe[1].Info.Petxiset = 4;
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UsbPort20Afe[1].Info.Txiset = 0;
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UsbPort20Afe[1].Info.Predeemp = 3;
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UsbPort20Afe[1].Info.Pehalfbit = 0;
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UsbPort20Afe[2].Info.Petxiset = 4;
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UsbPort20Afe[2].Info.Txiset = 0;
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UsbPort20Afe[2].Info.Predeemp = 3;
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UsbPort20Afe[2].Info.Pehalfbit = 0;
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UsbPort20Afe[3].Info.Petxiset = 4;
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UsbPort20Afe[3].Info.Txiset = 0;
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UsbPort20Afe[3].Info.Predeemp = 3;
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UsbPort20Afe[3].Info.Pehalfbit = 0;
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UsbPort20Afe[4].Info.Petxiset = 4;
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UsbPort20Afe[4].Info.Txiset = 0;
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UsbPort20Afe[4].Info.Predeemp = 3;
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UsbPort20Afe[4].Info.Pehalfbit = 0;
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UsbPort20Afe[5].Info.Petxiset = 4;
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UsbPort20Afe[5].Info.Txiset = 0;
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UsbPort20Afe[5].Info.Predeemp = 3;
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UsbPort20Afe[5].Info.Pehalfbit = 0;
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UsbPort20Afe[6].Info.Petxiset = 4;
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UsbPort20Afe[6].Info.Txiset = 0;
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UsbPort20Afe[6].Info.Predeemp = 3;
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UsbPort20Afe[6].Info.Pehalfbit = 0;
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UsbPort20Afe[7].Info.Petxiset = 4;
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UsbPort20Afe[7].Info.Txiset = 0;
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UsbPort20Afe[7].Info.Predeemp = 3;
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UsbPort20Afe[7].Info.Pehalfbit = 0;
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UsbPort20Afe[8].Info.Petxiset = 4;
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UsbPort20Afe[8].Info.Txiset = 0;
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UsbPort20Afe[8].Info.Predeemp = 3;
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UsbPort20Afe[8].Info.Pehalfbit = 0;
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UsbPort20Afe[9].Info.Petxiset = 4;
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UsbPort20Afe[9].Info.Txiset = 0;
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UsbPort20Afe[9].Info.Predeemp = 3;
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UsbPort20Afe[9].Info.Pehalfbit = 0;
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break;
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}
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//
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// Save USB2.0 AFE blobs
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//
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PcdSet32S (PcdUsb20Port0Afe, UsbPort20Afe[ 0].Blob);
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PcdSet32S (PcdUsb20Port1Afe, UsbPort20Afe[ 1].Blob);
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PcdSet32S (PcdUsb20Port2Afe, UsbPort20Afe[ 2].Blob);
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PcdSet32S (PcdUsb20Port3Afe, UsbPort20Afe[ 3].Blob);
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PcdSet32S (PcdUsb20Port4Afe, UsbPort20Afe[ 4].Blob);
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PcdSet32S (PcdUsb20Port5Afe, UsbPort20Afe[ 5].Blob);
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PcdSet32S (PcdUsb20Port6Afe, UsbPort20Afe[ 6].Blob);
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PcdSet32S (PcdUsb20Port7Afe, UsbPort20Afe[ 7].Blob);
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PcdSet32S (PcdUsb20Port8Afe, UsbPort20Afe[ 8].Blob);
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PcdSet32S (PcdUsb20Port9Afe, UsbPort20Afe[ 9].Blob);
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PcdSet32S (PcdUsb20Port10Afe, UsbPort20Afe[10].Blob);
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PcdSet32S (PcdUsb20Port11Afe, UsbPort20Afe[11].Blob);
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PcdSet32S (PcdUsb20Port12Afe, UsbPort20Afe[12].Blob);
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PcdSet32S (PcdUsb20Port13Afe, UsbPort20Afe[13].Blob);
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PcdSet32S (PcdUsb20Port14Afe, UsbPort20Afe[14].Blob);
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PcdSet32S (PcdUsb20Port15Afe, UsbPort20Afe[15].Blob);
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return EFI_SUCCESS;
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}
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/**
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Board GPIO Group Tier configuration init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integrer represent the board id.
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@retval EFI_SUCCESS The function completed successfully.
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**/
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EFI_STATUS
|
GpioGroupTierInit (
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IN UINT16 BoardId
|
)
|
{
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//
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// GPIO Group Tier
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//
|
|
switch (BoardId) {
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case BoardIdCometLakeULpddr3Rvp:
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PcdSet32S (PcdGpioGroupToGpeDw0, GPIO_CNL_LP_GROUP_GPP_G);
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PcdSet32S (PcdGpioGroupToGpeDw1, GPIO_CNL_LP_GROUP_SPI);
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PcdSet32S (PcdGpioGroupToGpeDw2, GPIO_CNL_LP_GROUP_GPP_E);
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break;
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default:
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PcdSet32S (PcdGpioGroupToGpeDw0, 0);
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PcdSet32S (PcdGpioGroupToGpeDw1, 0);
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PcdSet32S (PcdGpioGroupToGpeDw2, 0);
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break;
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}
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return EFI_SUCCESS;
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}
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|
/**
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GPIO init function for PEI pre-memory phase.
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@param[in] BoardId An unsigned integrer represent the board id.
|
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@retval EFI_SUCCESS The function completed successfully.
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**/
|
EFI_STATUS
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GpioTablePreMemInit (
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IN UINT16 BoardId
|
)
|
{
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//
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// GPIO Table Init.
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//
|
switch (BoardId) {
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case BoardIdCometLakeULpddr3Rvp:
|
PcdSet32S (PcdBoardGpioTablePreMem, (UINTN) mGpioTableCmlULpddr3PreMem);
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PcdSet16S (PcdBoardGpioTablePreMemSize, mGpioTableCmlULpddr3PreMemSize);
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PcdSet32S(PcdBoardGpioTableWwanOnEarlyPreMem, (UINTN) mGpioTableCmlULpddr3WwanOnEarlyPreMem);
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PcdSet16S(PcdBoardGpioTableWwanOnEarlyPreMemSize, mGpioTableCmlULpddr3WwanOnEarlyPreMemSize);
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PcdSet32S(PcdBoardGpioTableWwanOffEarlyPreMem, (UINTN) mGpioTableCmlULpddr3WwanOffEarlyPreMem);
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PcdSet16S(PcdBoardGpioTableWwanOffEarlyPreMemSize, mGpioTableCmlULpddr3WwanOffEarlyPreMemSize);
|
break;
|
|
default:
|
break;
|
}
|
|
return EFI_SUCCESS;
|
}
|
|
/**
|
PmConfig init function for PEI pre-memory phase.
|
|
@param[in] BoardId An unsigned integrer represent the board id.
|
|
@retval EFI_SUCCESS The function completed successfully.
|
**/
|
EFI_STATUS
|
PchPmConfigInit (
|
IN UINT16 BoardId
|
)
|
{
|
//
|
// Update PmCofig policy: output voltage of VCCPRIMCORE RAIL when SLP_S0# is asserted based on board HW design
|
// 1) Discete VR or Non Premium PMIC: 0.75V (PcdSlpS0Vm075VSupport)
|
// 2) Premium PMIC: runtime control for voltage (PcdSlpS0VmRuntimeControl)
|
// Only applys to board with PCH-LP. Board with Discrete PCH doesn't need this setting.
|
//
|
switch (BoardId) {
|
// Discrete VR solution
|
case BoardIdCometLakeULpddr3Rvp:
|
PcdSetBoolS (PcdSlpS0VmRuntimeControl, FALSE);
|
PcdSetBoolS (PcdSlpS0Vm070VSupport, FALSE);
|
PcdSetBoolS (PcdSlpS0Vm075VSupport, TRUE);
|
break;
|
|
default:
|
PcdSetBoolS (PcdSlpS0VmRuntimeControl, FALSE);
|
PcdSetBoolS (PcdSlpS0Vm070VSupport, FALSE);
|
PcdSetBoolS (PcdSlpS0Vm075VSupport, FALSE);
|
break;
|
}
|
|
return EFI_SUCCESS;
|
}
|
|
