/** @file
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Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
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Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/PcdLib.h>
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#include <Library/PlatformPciLib.h>
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UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000},
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{0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000}};
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UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000},
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{0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000}};
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UINT64 PCIE_PHY_BASE_1610 [PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000},
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{0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}};
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UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040},
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{0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}};
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PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
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{// HostBridge 0
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/* Port 0 */
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{
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0, //Segment
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PCI_HB0RB0_ECAM_BASE, //ecam
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0x80, //BusBase
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0x87, //BusLimit
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PCI_HB0RB0_IO_BASE, //IoBase
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(PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
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PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
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PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase
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(PCI_HB0RB0_PCI_BASE),//RbPciBar
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PCI_HB0RB0_PCIREGION_BASE, //PciRegionbase
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PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit
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},
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/* Port 1 */
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{
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1, //Segment
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PCI_HB0RB1_ECAM_BASE,//ecam
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0x90, //BusBase
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0x97, //BusLimit
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(PCI_HB0RB1_IO_BASE), //IoBase
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(PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit
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PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
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PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase
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(PCI_HB0RB1_PCI_BASE), //RbPciBar
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PCI_HB0RB1_PCIREGION_BASE, //PciRegionbase
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PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit
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},
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/* Port 2 */
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{
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2, //Segment
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PCI_HB0RB2_ECAM_BASE,
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0xF8, //BusBase
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0xFF, //BusLimit
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(PCI_HB0RB2_IO_BASE), //IOBase
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(PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit
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PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
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PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase
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(PCI_HB0RB2_PCI_BASE), //RbPciBar
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PCI_HB0RB2_PCIREGION_BASE, //PciRegionbase
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PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit
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},
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/* Port 3 */
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{
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3, //Segment
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PCI_HB0RB3_ECAM_BASE,
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0xb0, //BusBase
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0xb7, //BusLimit
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(PCI_HB0RB3_IO_BASE), //IoBase
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(PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1), //IoLimit
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PCI_HB0RB3_CPUMEMREGIONBASE,
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PCI_HB0RB3_CPUIOREGIONBASE,
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(PCI_HB0RB3_PCI_BASE), //RbPciBar
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PCI_HB0RB3_PCIREGION_BASE, //PciRegionbase
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PCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit
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},
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/* Port 4 */
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{
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4, //Segment
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PCI_HB0RB4_ECAM_BASE, //ecam
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0x88, //BusBase
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0x8f, //BusLimit
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PCI_HB0RB4_IO_BASE, //IoBase
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(PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimit
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PCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
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PCI_HB0RB4_CPUIOREGIONBASE, //CpuIoRegionBase
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(PCI_HB0RB4_PCI_BASE), //RbPciBar
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PCI_HB0RB4_PCIREGION_BASE, //PciRegionbase
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PCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit
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},
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/* Port 5 */
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{
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5, //Segment
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PCI_HB0RB5_ECAM_BASE,//ecam
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0x78, //BusBase
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0x7F, //BusLimit
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(PCI_HB0RB5_IO_BASE), //IoBase
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(PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimit
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PCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
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PCI_HB0RB5_CPUIOREGIONBASE, //CpuIoRegionBase
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(PCI_HB0RB5_PCI_BASE), //RbPciBar
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PCI_HB0RB5_PCIREGION_BASE, //PciRegionbase
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PCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit
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},
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/* Port 6 */
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{
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6, //Segment
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PCI_HB0RB6_ECAM_BASE,
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0xC0, //BusBase
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0xC7, //BusLimit
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(PCI_HB0RB6_IO_BASE), //IOBase
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(PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimit
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PCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
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PCI_HB0RB6_CPUIOREGIONBASE, //CpuIoRegionBase
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(PCI_HB0RB6_PCI_BASE), //RbPciBar
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PCI_HB0RB6_PCIREGION_BASE, //PciRegionbase
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PCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit
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},
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/* Port 7 */
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{
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7, //Segment
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PCI_HB0RB7_ECAM_BASE,
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0x90, //BusBase
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0x97, //BusLimit
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(PCI_HB0RB7_IO_BASE), //IoBase
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(PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1), //IoLimit
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PCI_HB0RB7_CPUMEMREGIONBASE,
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PCI_HB0RB7_CPUIOREGIONBASE,
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(PCI_HB0RB7_PCI_BASE), //RbPciBar
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PCI_HB0RB7_PCIREGION_BASE, //PciRegionbase
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PCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit
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}
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},
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{// HostBridge 1
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/* Port 0 */
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{
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8, //Segment
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PCI_HB1RB0_ECAM_BASE,
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0x80, //BusBase
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0x87, //BusLimit
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PCI_HB1RB0_IO_BASE, //IoBase
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(PCI_HB1RB0_CPUIOREGIONBASE + PCI_HB1RB0_IO_SIZE - 1), //IoLimit
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PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
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PCI_HB1RB0_CPUIOREGIONBASE, //CpuIoRegionBase
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(PCI_HB1RB0_PCI_BASE), //RbPciBar
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PCI_HB1RB0_PCIREGION_BASE, //PciRegionbase
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PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit
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},
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/* Port 1 */
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{
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9, //Segment
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PCI_HB1RB1_ECAM_BASE,
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0x90, //BusBase
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0x97, //BusLimit
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PCI_HB1RB1_IO_BASE, //IoBase
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(PCI_HB1RB1_CPUIOREGIONBASE + PCI_HB1RB1_IO_SIZE - 1), //IoLimit
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PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
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PCI_HB1RB1_CPUIOREGIONBASE, //CpuIoRegionBase
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(PCI_HB1RB1_PCI_BASE), //RbPciBar
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PCI_HB1RB1_PCIREGION_BASE, //PciRegionbase
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PCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit
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},
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/* Port 2 */
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{
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0xa, //Segment
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PCI_HB1RB2_ECAM_BASE,
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0x10, //BusBase
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0x1f, //BusLimit
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PCI_HB1RB2_IO_BASE, //IoBase
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(PCI_HB1RB2_CPUIOREGIONBASE + PCI_HB1RB2_IO_SIZE - 1), //IoLimit
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PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
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PCI_HB1RB2_CPUIOREGIONBASE, //CpuIoRegionBase
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(PCI_HB1RB2_PCI_BASE), //RbPciBar
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PCI_HB1RB2_PCIREGION_BASE, //PciRegionbase
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PCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit
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},
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/* Port 3 */
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{
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0xb, //Segment
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PCI_HB1RB3_ECAM_BASE,
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0xb0, //BusBase
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0xb7, //BusLimit
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PCI_HB1RB3_IO_BASE, //IoBase
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(PCI_HB1RB3_CPUIOREGIONBASE + PCI_HB1RB3_IO_SIZE - 1), //IoLimit
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PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase
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PCI_HB1RB3_CPUIOREGIONBASE, //CpuIoRegionBase
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(PCI_HB1RB3_PCI_BASE), //RbPciBar
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PCI_HB1RB3_PCIREGION_BASE, //PciRegionbase
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PCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit
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},
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/* Port 4 */
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{
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0xc, //Segment
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PCI_HB1RB4_ECAM_BASE,
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0x20, //BusBase
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0x2f, //BusLimit
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PCI_HB1RB4_IO_BASE, //IoBase
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(PCI_HB1RB4_CPUIOREGIONBASE + PCI_HB1RB4_IO_SIZE - 1), //IoLimit
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PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
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PCI_HB1RB4_CPUIOREGIONBASE, //CpuIoRegionBase
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(PCI_HB1RB4_PCI_BASE), //RbPciBar
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PCI_HB1RB4_PCIREGION_BASE, //PciRegionbase
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PCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit
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},
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/* Port 5 */
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{
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0xd, //Segment
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PCI_HB1RB5_ECAM_BASE,
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0x30, //BusBase
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0x3f, //BusLimit
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PCI_HB1RB5_IO_BASE, //IoBase
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(PCI_HB1RB5_CPUIOREGIONBASE + PCI_HB1RB5_IO_SIZE - 1), //IoLimit
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PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
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PCI_HB1RB5_CPUIOREGIONBASE, //CpuIoRegionBase
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(PCI_HB1RB5_PCI_BASE), //RbPciBar
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PCI_HB1RB5_PCIREGION_BASE, //PciRegionbase
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PCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit
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},
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/* Port 6 */
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{
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0xe, //Segment
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PCI_HB1RB6_ECAM_BASE,
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0xa8, //BusBase
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0xaf, //BusLimit
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PCI_HB1RB6_IO_BASE, //IoBase
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(PCI_HB1RB6_CPUIOREGIONBASE + PCI_HB1RB6_IO_SIZE - 1), //IoLimit
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PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
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PCI_HB1RB6_CPUIOREGIONBASE, //CpuIoRegionBase
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(PCI_HB1RB6_PCI_BASE), //RbPciBar
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PCI_HB1RB6_PCIREGION_BASE, //PciRegionbase
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PCI_HB1RB6_PCIREGION_BASE + PCI_HB1RB6_PCIREGION_SIZE - 1 //PciRegionlimit
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},
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/* Port 7 */
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{
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0xf, //Segment
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PCI_HB1RB7_ECAM_BASE,
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0xb8, //BusBase
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0xbf, //BusLimit
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PCI_HB1RB7_IO_BASE, //IoBase
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(PCI_HB1RB7_CPUIOREGIONBASE + PCI_HB1RB7_IO_SIZE - 1), //IoLimit
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PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase
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PCI_HB1RB7_CPUIOREGIONBASE, //CpuIoRegionBase
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(PCI_HB1RB7_PCI_BASE), //RbPciBar
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PCI_HB1RB7_PCIREGION_BASE, //PciRegionbase
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PCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit
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}
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}
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};
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