/** @file
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*
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* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
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* Copyright (c) 2016, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <Uefi.h>
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#include <PiPei.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/CacheMaintenanceLib.h>
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#include <PlatformArch.h>
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#include <Library/PlatformSysCtrlLib.h>
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#include <Library/OemMiscLib.h>
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#include <Library/OemAddressMapLib.h>
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#include <Library/ArmLib.h>
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#define PERI_SUBCTRL_BASE (0x40000000)
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#define MDIO_SUBCTRL_BASE (0x60000000)
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#define PCIE2_SUBCTRL_BASE (0xA0000000)
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#define PCIE0_SUBCTRL_BASE (0xB0000000)
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#define ALG_BASE (0xD0000000)
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#define SC_BROADCAST_EN_REG (0x16220)
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#define SC_BROADCAST_SCL1_ADDR0_REG (0x16230)
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#define SC_BROADCAST_SCL1_ADDR1_REG (0x16234)
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#define SC_BROADCAST_SCL2_ADDR0_REG (0x16238)
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#define SC_BROADCAST_SCL2_ADDR1_REG (0x1623C)
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#define SC_BROADCAST_SCL3_ADDR0_REG (0x16240)
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#define SC_BROADCAST_SCL3_ADDR1_REG (0x16244)
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#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG (0x1000)
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#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG (0x1010)
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#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG (0x1014)
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#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (0x1018)
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#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (0x101C)
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#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG (0x1200)
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#define SC_ITS_M3_INT_MUX_SEL_REG (0x21F0)
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#define SC_TM_CLKEN0_REG (0x2050)
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#define SC_TM_CLKEN0_REG_VALUE (0x3)
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#define SC_BROADCAST_EN_REG_VALUE (0x7)
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#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE0 (0x0)
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#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE1 (0x40016260)
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#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE2 (0x60016260)
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#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE3 (0x400)
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#define SC_ITS_M3_INT_MUX_SEL_REG_VALUE (0x7)
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#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0 (0x0)
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#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0 (0x27)
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#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1 (0x2F)
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#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2 (0x77)
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#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0 (0x178033)
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#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0 (0x17003c)
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#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0 (0x15003d)
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#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1 (0x170035)
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#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0 (0x16003e)
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VOID PlatformTimerStart (VOID)
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{
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// Timer0 clock enable
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MmioWrite32 (PERI_SUBCTRL_BASE + SC_TM_CLKEN0_REG, SC_TM_CLKEN0_REG_VALUE);
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}
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void QResetAp(VOID)
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{
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MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
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(void)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
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ArmDataSynchronizationBarrier ();
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ArmInstructionSynchronizationBarrier ();
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//SCCL A
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if (!PcdGet64 (PcdTrustedFirmwareEnable))
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{
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StartUpBSP ();
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}
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}
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EFI_STATUS
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EFIAPI
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EarlyConfigEntry (
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IN EFI_PEI_FILE_HANDLE FileHandle,
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IN CONST EFI_PEI_SERVICES **PeiServices
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)
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{
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DEBUG((EFI_D_INFO,"SMMU CONFIG........."));
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(VOID)SmmuConfigForOS();
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DEBUG((EFI_D_INFO,"Done\n"));
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DEBUG((EFI_D_INFO,"AP CONFIG........."));
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(VOID)QResetAp();
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DEBUG((EFI_D_INFO,"Done\n"));
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DEBUG((EFI_D_INFO,"MN CONFIG........."));
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(VOID)MN_CONFIG();
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DEBUG((EFI_D_INFO,"Done\n"));
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if(OemIsMpBoot())
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{
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DEBUG((EFI_D_INFO,"Event Broadcast CONFIG........."));
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//EVENT broadcast
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MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
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MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
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MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
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MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
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MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
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MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
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MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
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MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
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MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
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MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
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MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
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MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
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MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
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MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
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MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
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MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
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MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
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MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
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MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
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MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
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MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
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MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
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MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
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MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
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MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
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MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
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MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
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MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
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DEBUG((EFI_D_INFO,"Done\n"));
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}
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DEBUG((EFI_D_INFO,"PCIE RAM Address CONFIG........."));
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if(OemIsMpBoot())
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{
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MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0);
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MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0);
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MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1);
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MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0);
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MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1);
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}
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else
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{
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MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_REMAP_CTRL_REG, PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0);
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MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2);
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MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0);
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MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0);
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MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0);
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}
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DEBUG((EFI_D_INFO,"Done\n"));
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MmioWrite32(ALG_BASE + SC_ITS_M3_INT_MUX_SEL_REG, SC_ITS_M3_INT_MUX_SEL_REG_VALUE);
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DEBUG((EFI_D_INFO,"Timer CONFIG........."));
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PlatformTimerStart ();
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DEBUG((EFI_D_INFO,"Done\n"));
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return EFI_SUCCESS;
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}
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