/** @file
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*
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* Copyright (c) 2011-2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <ArmPlatform.h>
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#define DP_BASE_DESCRIPTOR ((FixedPcdGet64 (PcdArmMaliDpBase) != 0) ? 1 : 0)
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// Number of Virtual Memory Map Descriptors
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#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (14 + DP_BASE_DESCRIPTOR)
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// DDR attributes
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#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
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#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
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/**
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Return the Virtual Memory Map of your platform
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This Virtual Memory Map is used by MemoryInitPei Module to initialize
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the MMU on your platform.
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@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR
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describing a Physical-to-Virtual Memory
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mapping. This array must be ended by a
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zero-filled entry.
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**/
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VOID
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ArmPlatformGetVirtualMemoryMap (
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IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
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)
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{
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ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
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EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
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UINTN Index = 0;
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ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
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UINT32 SysId;
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BOOLEAN HasSparseMemory;
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EFI_VIRTUAL_ADDRESS SparseMemoryBase;
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UINT64 SparseMemorySize;
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ASSERT (VirtualMemoryMap != NULL);
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// The FVP model has Sparse memory
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SysId = MmioRead32 (ARM_VE_SYS_ID_REG);
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if (SysId != ARM_RTSM_SYS_ID) {
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HasSparseMemory = TRUE;
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ResourceAttributes =
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED;
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// Declared the additional DRAM from 2GB to 4GB
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SparseMemoryBase = 0x0880000000;
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SparseMemorySize = SIZE_2GB;
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
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ResourceAttributes,
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SparseMemoryBase,
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SparseMemorySize);
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} else {
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HasSparseMemory = FALSE;
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SparseMemoryBase = 0x0;
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SparseMemorySize = 0x0;
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}
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VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)
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AllocatePages (EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR)
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* MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
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if (VirtualMemoryTable == NULL) {
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return;
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}
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CacheAttributes = DDR_ATTRIBUTES_CACHED;
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// ReMap (Either NOR Flash or DRAM)
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VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// DDR
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// CPU peripherals. TRM. Manual says not all of them are implemented.
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// SMB CS0-CS1 - NOR Flash 1 & 2
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// SMB CS2 - SRAM
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// Peripheral CS2 and CS3
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;
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VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// Map region for the framebuffer in the system RAM if no VRAM present
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if (FixedPcdGet32 (PcdArmLcdDdrFrameBufferBase) == 0) {
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// VRAM
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VirtualMemoryTable[++Index].PhysicalBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;
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VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;
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VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE;
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//
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// Map the VRAM region as Normal Non-Cacheable memory and not device memory,
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// so that we can use the accelerated string routines that may use unaligned
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// accesses or DC ZVA instructions. The enum identifier is slightly awkward
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// here, but it maps to a memory type that allows buffering and reordering.
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//
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
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} else {
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ASSERT ((ARM_VE_DRAM_BASE + ARM_VE_DRAM_SZ - 1) <
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FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase));
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VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase);
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VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase);
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VirtualMemoryTable[Index].Length = FixedPcdGet32 (PcdArmLcdDdrFrameBufferSize);
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// Map as Normal Non-Cacheable memory, so that we can use the accelerated
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// SetMem/CopyMem routines that may use unaligned accesses or
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// DC ZVA instructions. If mapped as device memory, these routine may cause
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// alignment faults.
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// NOTE: The attribute value is misleading, it indicates memory map type as
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// an un-cached, un-buffered but allows buffering and reordering.
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
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}
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if (FixedPcdGet64 (PcdArmMaliDpBase) != 0) {
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// DP500/DP550/DP650 peripheral memory region
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VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdArmMaliDpBase);
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VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdArmMaliDpBase);
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VirtualMemoryTable[Index].Length = FixedPcdGet32 (PcdArmMaliDpMemoryRegionLength);
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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}
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// Map the PCI configration and memory space if the platform is FVP RevC.
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if ((SysId & ARM_FVP_SYS_ID_REV_MASK) == ARM_FVP_BASE_REVC_REV) {
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// SMMUv3
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VirtualMemoryTable[++Index].PhysicalBase = FVP_REVC_SMMUV3_BASE;
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VirtualMemoryTable[Index].VirtualBase = FVP_REVC_SMMUV3_BASE;
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VirtualMemoryTable[Index].Length = FVP_REVC_SMMUV3_SIZE;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// PCI Configuration Space
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VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
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VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
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VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExpressBaseSize);
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// PCI Memory Space
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VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet32 (PcdPciMmio32Base);
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VirtualMemoryTable[Index].VirtualBase = FixedPcdGet32 (PcdPciMmio32Base);
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VirtualMemoryTable[Index].Length = FixedPcdGet32 (PcdPciMmio32Size);
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// 64-bit PCI Memory Space
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VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciMmio64Base);
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VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciMmio64Base);
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VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciMmio64Size);
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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}
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// Map sparse memory region if present
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if (HasSparseMemory) {
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VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase;
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VirtualMemoryTable[Index].VirtualBase = SparseMemoryBase;
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VirtualMemoryTable[Index].Length = SparseMemorySize;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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}
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VirtualMemoryTable[++Index].PhysicalBase = SBSA_WATCHDOG_BASE;
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VirtualMemoryTable[Index].VirtualBase = SBSA_WATCHDOG_BASE;
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VirtualMemoryTable[Index].Length = SBSA_WATCHDOG_SIZE;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// End of Table
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VirtualMemoryTable[++Index].PhysicalBase = 0;
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VirtualMemoryTable[Index].VirtualBase = 0;
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VirtualMemoryTable[Index].Length = 0;
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VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
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ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
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*VirtualMemoryMap = VirtualMemoryTable;
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}
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